Nilesh Pathrabe — CEO
As a Design verification Engineer, I'm problem-solver with a passion for ensuring that electronic products function correctly before they are manufactured with 2yrs of experience in these field. I have a strong background in SV & UVM & also had a hands on experience in Designing using verilog. I'm skilled in Questa , Vsim, & vivado. I'm always seeking to learn & grow in my VLSI dream field. Technical Summary :- ---------------------------------- • Hands-on experience in UVM and System Verilog Test-Bench development and analysis. • Hands on experience on developing all the test bench components in SV and UVM. • Experience in UVM based protocol Verification. • Experience in System Verilog based protocol Verification. • Experienced in developing Test cases, Functional coverage • Familiar with OOPs concept of System Verilog. • Familiar with system Verilog functional coverage. • Familiar with system Verilog assertions. • Knowledge of UVM callbacks. • Knowledge of RAL (Register abstractions layer). • Hands on experience of Verilog. • Good Knowledge of ASIC Design flow & Digital electronics Verilog Projects :- ---------------------------- *Designing of UART , SPI, PWM signals, BIST for SW & LED , I2C, SRAM , Synchronous FIFO. SV & UVM Projects :- -------------------------------- *Worked on verification of synchronous FIFO using System verilog & UVM. *Worked on verification of SRAM using System verilog & UVM. *Worked on Verification of APB_RAM , AHB, AXI, SPI, I2C, UART, protocols verification using system verilog & UVM. *Having the Knowledge of Constrained random Driven verification & Assertion based verification. I'm looking for more opportunities in Design verification Enginner. Please feel free to contact me for further infromation. nileshpathrabe@zohomail.in || Nagpur 440002 , India Thank you for reading my career summary.
Stackforce AI infers this person is a Design Verification Engineer specializing in electronic product verification and VLSI design.
Location: Nagpur, Maharashtra, India
Experience: 0 mo
Career Highlights
- 2 years of hands-on experience in design verification.
- Proficient in UVM and System Verilog methodologies.
- Skilled in designing and verifying complex electronic protocols.
Education
Bachelor of Technology - B.Tech at JD College of Engineering, Khandala