Rajeev Varshney — Software Engineer

Proficient in designing and implementing high-performance System on Chip (SoC) IPs using industry-standard design methodologies and tools. Skilled in developing and integrating Network on Chip (NoC) architectures into complex SoC designs to enable efficient communication between on-chip components. Experienced in optimizing SoC IP designs for power, area, and performance to meet specific customer requirements and industry standards. Strong background in RTL design, verification, synthesis, and timing closure of SoC IPs and NoC components. Proficient in using EDA tools such as Synopsys Design Compiler, NC sim, HAL, and conformal to develop and verify SoC IP and NoC designs. Experienced in developing and using performance analysis and optimization tools for SoC IPs and NoCs to achieve optimal system-level performance. Collaborative team player with excellent communication skills, able to work effectively with cross-functional teams and stakeholders to deliver high-quality SoC IP and NoC designs. Passionate about advancing technology and innovation in the semiconductor industry, always seeking to learn and stay up-to-date on the latest trends and developments.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in semiconductor technology and system-on-chip architectures.

Location: Bengaluru, Karnataka, India

Experience: 12 yrs 2 mos