Shreyas Jinadatta

Software Engineer

Chandler, Arizona, United States8 yrs 4 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Analog and Mixed-Signal IC Design.
Proven track record in PMIC design and validation.
Strong proficiency in Cadence tools for circuit design.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Analog and Mixed-Signal IC design.

Contact

Skills

Core Skills

Integrated Circuit DesignAnalog Circuit DesignTestingAnalog ValidationPower Management IcPhysical Design

Other Skills

Analog CircuitsC (Programming Language)C++CMOSCadence ADEXL/MaestroCadence SpectreCadence VirtuosoCadence Virtuoso Layout EditorCircuit AnalysisCircuit DesignClock Tree synthesisData analysisDebuggingElectronic System DesignElectronics

About

I am currently working as an Analog Design Engineer at Texas Instruments in the Buck Switching Regulator (Wide Vin) team located in Phoenix, AZ. I'm a Masters graduate from Texas A&M University, with Analog and Mixed-signal design as my major. I have completed Advanced Analog IC Design, High-speed IO design, PMIC Circuits and Systems Design, VLSI IC Design, RFIC Design and PLL design courses as part of my graduate coursework. I interned as an Analog Design Engineer Co-op at Skyworks Solutions Inc. in the CMOS PA Controller group during the Summer and Fall of 2020 working on design improvements to a voltage-to-current converter. My previous work experience was as an Analog Validation Engineer of Power Management IC (PMIC) and as a Physical Design Engineer at Qualcomm (Bangalore) for 3 years. I have also worked on multiple Analog/Mixed-Signal Circuit Design projects during my graduate and undergraduate studies.

Experience

Texas instruments

Analog Design Engineer

Jun 2021 – Present · 4 yrs 9 mos · Phoenix, Arizona, United States

PMIC design engineer in the Buck Switching Regulator Wide Vin team

Integrated Circuit DesignCadence VirtuosoAnalog Circuit Design

Skyworks solutions, inc.

Analog Design Engineer Co-op

May 2020 – Dec 2020 · 7 mos · Cedar Rapids, Iowa, United States

Design optimization of the Voltage to Current converter block to create a design template, working on the voltage reference generation and the resistor trim block design, and enhancing the turn-on time and current accuracy.
Post-silicon verification and testing of standalone CMOS die which included generating lab testing scripts to automate the chip testing process, collecting and analyzing the testing data.
Gained Cadence proficiency in using ADEXL/Maestro tool, simulation efficiency in Spectre (APS/XPS) and simulation skills in Monte Carlo, and PVT corners analysis.

Voltage to Current converter designVoltage reference generationResistor trim block designPost-silicon verificationTesting scripts generationData analysis+6

Qualcomm bdc

3 roles

Analog Validation Engineer

Promoted

Aug 2017 – Jul 2019 · 1 yr 11 mos

PMIC Systems and Validation Engineer :
System definition and Post-silicon Verification owner of User Interface modules (Display, RGB driver and Haptics) in Qualcomm Power Management Integrated Circuits across 5 projects.
Found critical bugs in display bias module and played a key role in fixing the issue working with multiple stakeholders preventing a second revision of the project.
Worked closely with the Display design team in resolving customer issues in LCD bias module.

Analog ValidationPower Management IC

Associate Engineer

Jul 2016 – Aug 2017 · 1 yr 1 mo

Physical Design Engineer :
Implemented physical design of low power blocks in 7nm and 10nm technology nodes.
Tasks involved Floor-planning, Placement, Clock Tree synthesis, Routing, Timing analysis and Signoff closure (Formal, CLP, Redhawk and Physical Verification).

Physical designFloor-planningPlacementClock Tree synthesisRoutingTiming analysis+3