May 2014 – Jul 2014 · 2 mos · Bengaluru, Karnataka, India

• Timing Critique Module
• 1. The project aimed to analyse critical path of Modem SOC (system on chip) and report cell delays and wire delays. Also to segregate delays pertaining to each cell variant and group delays within each PD block. Synopsys Prime Time tool was used and script was written in Tcl.
• 2. The second project was to find the delay of cell at some intermediate operating voltage which has better correlation with spice results. So that the script to fix setup and hold violation take less iterations.