Chepuru Manohar Sai — Software Engineer

• Working in MediaTek as a part of Design verification team • Responsible for verification of SoC's at chip level and Verification of IP’s using UVM and C. • Built UVM testbenches for many Peripheral IPs like Keypad, Infrared Receiver, Enhanced SPI(eSPI) from scratch • Currently working on verification of Audio Subsystem and GPU compression and decompression technologies of ARM’s and Imagination Technologies IPs. • I have good experience with the EDA tools like Cadence Virtuoso, Xcelium, Synopsys VCS, DC, Verdi, Primetime, Mentor Graphics Questa sim, Model sim, Altera Quartus. • I did digital projects based on Verilog HDL, Scripting projects based on Perl, Design projects in Cadence Virtuoso, worked on DE2-115 FPGA Board and a project on complete ASIC flow (RTL to GDSII) involving various EDA tools. • At Present I'm working as a Design Verification Engineer at MediaTek, Bangalore. TECHNICAL SKILLS • SOC Verification • NOC Verification • Subsys Verification • IP Verification • System Verilog • Verilog • UVM • Protocol : AXI, AHB, APB, Infrared Protocols, Serial Protocols • C Language • Scripting Language : Perl, TCL and Python • Waveform tools : Verdi. • I am a Machine Learning and Technology Enthusiast.

Stackforce AI infers this person is a VLSI Design Verification Engineer with expertise in SoC and IP verification.

Experience: 4 yrs 9 mos