Raghava Madem — Software Engineer

• 3 years of experience in Block/IP level RTL Design. Responsible for developing different digital modules/IPs for 4G/5G Sub6 & 5G mmWave RFIC chips. • Hands on experience in RTL Design and Implementation flows, Verilog Coding and python scripting. • Strong fundamentals in Microarchitecture, Digital Design and RTL Coding Responsible for following front end activities: • Individual ownership of Digital Design for various IP cores like RF Interconnect bus and TX/RX Register Digital Top blocks. • Proper understanding of the high-level architecture, functionality and connectivity of cores. • Responsible for defining microarchitecture as per design specification from systems and analog teams. • Block level RTL coding using Verilog. • Low power design of Digital Top modules and UPF Design. • Running block level Quality checks like Lint, CDC, Conformal Low power checks. • Running Synthesis, generating timing constraints and optimal DC netlist meeting QoR (Timing, Power & Area) and deliver to PD team. • Running various implementation tools like STA, LEC, Conformal ECO. • Timely and bug free delivery of RTL and Netlist to SoC and PD teams. Developed new automated flow for Scan stitching of ECO flops using Python: • Conformal ECO tool cannot do scan stitching for flops inserted through ECO. I developed an automation flow based on Python for scan stitching of ECO flops to avoid manual stitching and errors, which also dumps scan def.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in RTL Design and Low Power VLSI for telecommunications.

Location: Bengaluru, Karnataka, India

Experience: 4 yrs 6 mos