R

Raghav Rastogi

Product Engineer

Gurgaon, Haryana, India0 mo experience

Key Highlights

  • Expert in SystemVerilog and UVM for ASIC verification.
  • Developed multi-environment testing scenarios for interconnects.
  • Hands-on experience with RISC-V architecture and verification.
Stackforce AI infers this person is a Design and Verification Engineer specializing in ASIC and microprocessor verification.

Contact

LinkedIn

Skills

Core Skills

Universal Verification Methodology (uvm)Systemverilog

Other Skills

.NET Framework5 stage pipelined microprocessorAMBA (AXI, APB, AHB, and AXI4 Stream)AMBA AHBAMBA APBAMBA AXIApplication-Specific Integrated Circuits (ASIC)AutomationBashC (Programming Language)DisplayPort (2.0, 1.x)Functional VerificationGitHardware VerificationInterconnects/Crossbars

Experience

Full-time

Siemens EDA (Siemens Digital Industries Software)

– Present · helped me get this job

Full-time

Truechip Solutions

– Present

Meta

ASIC Engineer, Design Verification

May 2025 – Present · 10 mos · Bangalore Urban, Karnataka, India · Hybrid

  • At Meta, I focus on the design verification of debug subsystems that support AI inference and data center chip functionalities. My role involves collaborating with cross functional teams to streamline verification processes and enhance system reliability.
Universal Verification Methodology (UVM)Hardware VerificationAMBA AHBFunctional VerificationAMBA APBSystemVerilog+4

3st technologies

Design Intern

Jan 2019 – Apr 2019 · 3 mos · Noida Area, India

Universal Verification Methodology (UVM)Object-Oriented Programming (OOP)Hardware VerificationLinuxBashPython (Programming Language)+9

Microtek international private limited delhi

Intern

Jun 2018 – Jul 2018 · 1 mo · Udyog Nagar, Delhi

C (Programming Language)

Education

Manav Rachna University

Bachelor of Technology (B.Tech.)

Jan 2015 – Jan 2019

DAV Public School, Sector 14, Gurgaon

Science (PCM)

Jan 2013 – Jan 2015

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