Abhilash M

Software Engineer

Bengaluru, Karnataka, India2 yrs 4 mos experience

Key Highlights

  • Proficient in SystemVerilog and UVM for digital verification.
  • Experience in designing and verifying complex digital circuits.
  • Internship focused on developing Verification IPs for protocols.
Stackforce AI infers this person is a Verification Engineer with expertise in digital design and verification methodologies.

Contact

LinkedIn

Skills

Core Skills

SystemverilogUniversal Verification Methodology (uvm)

Other Skills

APBBasic unix commandsBasics of tool command languageDigital ElectronicsSynopsis vcsSynopsys VCS toolVerilog

Experience

Siliconsemislice

Verification Engineer

Sep 2025 – Present · 6 mos · Bengaluru, Karnataka, India · On-site

Risetime semiconductors

Design verification Intern

Sep 2024 – Aug 2025 · 11 mos · Bengaluru, Karnataka, India · On-site

  • Built Verification IP's for Quad SPI protocol.

Sumedhait

Design verification Trainee

Sep 2023 – Aug 2024 · 11 mos · Bengaluru, Karnataka, India · On-site

  • Design of all digital circuits, memories, verification of memories using System verilog and UVM, APB slave verification using System verilog and UVM, 16X16 router verification using System verilog and UVM.
SystemVerilogUniversal Verification Methodology (UVM)APBDigital Electronics

Education

RNS Institute of Technology - India

Bachelor of Engineering - BE — Electrical and Electronics Engineering

Jan 2019 – Jan 2023

Narayana PU college Ballari

Pre university course — PCMC

Aug 2017 – Apr 2019

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