Jul 2022 – Nov 2022 · 4 mos · Noida, Uttar Pradesh, India

• 1. Core Member of CXL Verification IP R&D team. 2. Key contributor to development of new features in CXL 2.0 and beginner in CXL 3.
• 3. Responsible for timely resolving of Jiras for critical customers.
• 4. Jira solving buddy for team members.

May 2020 – Jul 2022 · 2 yrs 2 mos · Noida, Uttar Pradesh, India

• 1. Member of PCIe/CXL Verification IP R&D team.
• 2. Responsible for developing and verifying the VIPs for appropriate functionality.
• 3. Responsible for handling CXL TL.mem layer and APN with special attention.
• 4. Worked in Customer support for different CXL issues.
• 5. Developed system VIP APIs for PCIe protocol from scratch.
• 6. Member of Toastmasters club.
• 7. Organised many team-building activities for local and global team.
• 8. Mentored many new members to the team across locations.

May 2019 – Jul 2019 · 2 mos · Noida, India

• 1. Designed and implemented electronic blocks in Verilog.
• 2. System design and verification using System Verilog.
• 3. Understanding in UVM.
• 4. Usage of Questa tool.
• 5. UART, RISC
• 6. Implemented LC3 and SV testbench.