Jan 2023 – Present · 3 yrs 2 mos · California City, California, United States · Remote

• Building head up display and aviation hacks and Operating airplanes.

Nov 2022 – May 2025 · 2 yrs 6 mos

• Adding Automotive characteristics and functional safety schemes to UCIe Chiplet interconnects

Jun 2022 – Mar 2025 · 2 yrs 9 mos

• Mercedes Benz P44 training for management.
• Assembling the future of Autonomous Driving with Silicon.
• Putting together multiple heterogeneous systems in one chip.
• mSoC: multiple System on Chip.

Jan 2019 – Jun 2022 · 3 yrs 5 mos

• Making Autonomous Driving Level 4 affordable
• Chip design and Floor Plan, Overall architecture of the System on Chip, Custom IP design.
• TCL & Co.
• Synopsys Platform Architect
• Entertainment Chip system architecture.
• Cadence tooling / Xtensa / Synopsys Platform Architect / Mentor Graphic Siemens Catapult HLSV / Icarus Verilog.
• Characterization of the workload and creation of IP blocks.
• Hardware/Software architect, Vehicle Intelligence.
• Certified Autonomous Car Safety driver for California. (ATV driver)
• Manage Development of custom hardware and GPU
• RTL and Verilog , overall architecture, Cadence Software and Synopsis.
• Hardware simulation.
• Manage Silicon vendor relationship and prototyping
• Autonomous Driving Algorithms conversion to hardware.

Dec 1997 – Nov 2017 · 19 yrs 11 mos

• Performance/Principal System Architect, Intel Corporation
• 3 Intel Achievement Awards for technical Achievements , (Highest Intel Award, less than 0.1% of Intel employees can claim 3 ;-) )
• Processor Contributions:
• ▪ CPU – Katmai, Willamette, Prescott, Cedar Mill, Merom/Conroe, Penryn, Nehalem
• ▪ SoC – Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, KabyLake, Skylake-X, and performance advisory role on Atom Product line.
• Architecture Planning/Studies:
• Introduced replacement roadmap of the Pentium 4 to Core (tm) microarchitecture using data to articulate real programs to demonstrate the changes needed to Intel management. Direct interaction with Paul Otellini (CEO). Acted as one of his technical performance advisors and called upon when difficult decisions were required.
• The latter resulted in Intel Corp regaining performance leadership.
• Architectural Tuning:
• Worked and managed instruction set optimization and design of instructions, VIP video codec programming, and offloading of video codec to custom hardware. It positioned Intel as the current leader in video encoding ahead of the competition.
• Early SIMD coder from 64 bits, in 2000, to 512 bits AVX512, in 2017.
• Android X86 platform tuning to reduce lag via robotics and code analysis. The latter fixed the user experience of Android on Intel Processors.
• Multimedia instructions planning and optimization in collaboration with DivX team with the goal of outperforming existing codec. Achieved outstanding performance at video encoding and secured Intel performance leadership in the arena (instructions MPSADBW & PHMINPOSUW).
• Drove and managed the development of touch screen evaluation methodologies and tuned Tier1 Ultrabooks (Acer, Lenovo, Dell, Toshiba, ThinkPad) which enabled Intel touch technology to match Apple IOS touch experience.
• Modesty is off on linkedin.

Dec 1997 – Nov 2017 · 19 yrs 11 mos

• Leadership
• ∙ Principal Engineer at Intel Corporation.
• ∙ Lead and mentor to a team of 45 experts in processor performance, power analysis, sub-system optimization (instruction to platform).
• ∙ Lead for touch adoption/experience validation of the PC platform between Intel and Microsoft.
• ∙ Father of the Intel Skulltrail Platform and Extreme Edition Brand.
• ∙ Direct connections to Tier 1 press.
• ∙ Lead the performance transition from the Pentium 4 to Core 2 Duo later generations.
• ∙ Lead Performance optimization of Pentium 4, DivX and Povray optimizations, from Business management to coding itself.
• ∙ Started and established 3Dmark as a performance matrix, from coding the processor libraries in the Max Payne Engine to plugging them into 3Dmark (1997 to 2002)
• Master minded the Intel vs ARM answer http://www.anandtech.com/show/6529/busting-the-x86-power-myth-indepth-clover-trail-power-analysis
• 1997-Dec 1999 Munich:
• Bluetooth 1st coding of Windows Stack, coding of the enumeration of property.
• 3DMark x86 library optimization for Intel CPUs.

Jan 1986 – Jan 2023 · 37 yrs

• Lieutenant, Armée de Terre (French Army)