Jan 2024 – Present · 2 yrs 2 mos · Palo Alto, California, United States · On-site

Aug 2019 – Jan 2024 · 4 yrs 5 mos · San Francisco Bay Area

Nov 2018 – Aug 2019 · 9 mos · Sunnyvale

• Stealth mode

Oct 2018 – Dec 2020 · 2 yrs 2 mos · San Francisco Bay Area

Sep 2017 – Oct 2018 · 1 yr 1 mo · San Francisco Bay Area

• Nagesh joins as Vice President of Engineering, after founding Auviz Systems, which he sold to Xilinx. At Xilinx, Nagesh directed teams focusing on deep learning and computer vision-based solutions for auto OEMs and tier 1 suppliers.
• Nagesh is charged with growing and leading the company’s global engineering efforts across various offices. His teams are developing several of the core technologies necessary for autonomous driving: localization, edge computing, perception, sensor fusion, synthetics, and augmented reality.

Aug 2016 – Sep 2017 · 1 yr 1 mo · San Francisco Bay Area

• Xilinx has acquired Auviz Systems to pave the way for leadership in Embedded Vision, Deep Learning and Computer Vision. I'm now leading this effort. I, along with the awesome team at Auviz have now joined Xilinx and are looking forward to continued success in the market as a part of Xilinx!

Oct 2013 – Sep 2015 · 1 yr 11 mos · Campbell, CA

• Auviz Systems is an Independent Software Vendor (ISV) that accelerates algorithms for the Data Center & Embedded Devices. We provide Middleware IP, Custom Accelerators and Services for application developers that require higher performance at lower power. Auviz Middleware IP (AuvizCV, AuvizLA and AuvizDNN) solves the problem of achieving good Quality of Results (QOR, i.e. performance, area, latency) from OpenCL and High Level Synthesis without having to know the details of the underlying Hardware Architecture. Targeting FPGA’s, Auviz Middleware enables software developers to program using their existing methodology - C/C++ with an OpenCL platform model. Auviz expertise in Machine Learning, Vision Algorithms, FPGA implementation, software development and applications uniquely positions us to help close the ‘programming gap’ for FPGA’s.

Mar 2010 – Jul 2013 · 3 yrs 4 mos

• o Business and customer development for Cadence FPGA System Planner (FSP)
• o Set the engineering direction and priorities for Cadence FPGA System Planner
• o Expand the FPGA footprint for Cadence Design Systems

Jan 2003 – Apr 2010 · 7 yrs 3 mos

• Founded Taray in 2003.
• Setup & managed India development center as well as US operations
• Memory Interface Generator for Xilinx (2003 to 2010)
• Cadence OEM's Taray 7Circuits.
• Taray was acquired by Cadence in March 2010

Jan 2000 – Jan 2002 · 2 yrs

• Manage engineering for wireless networking

Jan 1993 – Jan 2000 · 7 yrs

• Design and verify hardware for complex servers & processors

Jan 1989 – Jan 1992 · 3 yrs

• VLSI Design