Alok Ranjan Pandey

Software Engineer

Lucknow, Uttar Pradesh, India3 yrs 2 mos experience

Key Highlights

Over 2 years of experience in Physical Design Engineering.
Expertise in Static Timing Analysis and Physical Verification.
Hands-on experience with leading EDA tools and methodologies.

Stackforce AI infers this person is a VLSI and Embedded Systems Engineer with a focus on Physical Design.

Contact

Skills

Core Skills

Physical DesignStatic Timing AnalysisDigital Circuit Design

Other Skills

8051 MicrocontrollerARM Cortex-MApplication-Specific Integrated Circuits (ASIC)C (Programming Language)CMOSCTSCircuit DesignClock Tree SynthesisCongestion analysisEDAEM and SI AnalysisFloor PlanningFunctional VerificationIR-DropKeil

About

# Physical Design Engineer with 2+ years of Experience in PnR to GDSII, Layout and Mixed Signal Designs at block & full chip design. Expertise: Synthesis, Floor Planning, Placement, CTS, Congestion analysis, Routing, Static Timing Analysis and Closure, LEC, IR-Drop, EM and SI Analysis, Physical Verification (DRC/LVS/ERC) and Low power analysis.

Experience

Capgemini engineering

Physical Design Engineer

Sep 2021 – Sep 2023 · 2 yrs · Bengaluru, Karnataka, India

Engineering Research & Development Department of Semi-Conductors and Electronics Industry.
Skills: EDA · Digital Circuit Design · Clock Tree Synthesis · Logic Design · Circuit Design · CMOS · Physical Design · Application-Specific Integrated Circuits (ASIC) · System on a Chip (SoC) · Very-Large-Scale Integration (VLSI) · VLSI CAD · Perl · Synopsys Design Compiler · Synopsys IC Compiler · Synopsys Formality · Synopsys Primetime · TCL · Static Timing Analysis · PV Design · Microsoft PowerPoint · Public Speaking · Teamwork · Team Leadership · Verilog

EDADigital Circuit DesignClock Tree SynthesisLogic DesignCircuit DesignCMOS+18

Takshila institute of vlsi technologies

Physical Design Trainee

Mar 2021 – Aug 2021 · 5 mos

EDADigital Circuit DesignClock Tree SynthesisLogic DesignCircuit DesignCMOS+16

Isro - indian space research organization

2 roles

Student Researcher

Aug 2019 – May 2020 · 9 mos

Project Title: speed and position control mechanism for satellite imaging applications.
Description: Speed and control is an important issue that has been widely used in satellite imaging
applications. However, it is still a big challenge to achieve both purposes of full speed and torque
balance. The proposed design considers the coverage problem for speed and position control
mechanism. The main aims of this mechanism to balance the speed and power consumptions and power can be easily exhausted almost at the same time.