Raja Mondal

CEO

Bangalore Urban, Karnataka, India8 yrs 1 mo experience
Highly Stable

Key Highlights

  • 8 years of experience in physical design.
  • Expertise in Clock Tree Synthesis and Static Timing Analysis.
  • Hands-on experience with multiple tape-outs and deployments.
Stackforce AI infers this person is a Physical Design Engineer with expertise in semiconductor technology.

Contact

Skills

Other Skills

7nmFusion compilerICC2INNOVUSPerlPhysical DesignStatic Timing AnalysisTCL

About

Having 8 yrs of Industrial experience in physical Design. Hands on experience in 4 tape-outs and 5 deployments with varying nodes that includes GF14nm and TSMC 7nm and TSMC 5nm TSMC 3nm TSMC N3E hybrid row and SF2 /SF3 technology N2P Expertise in Clock Tree Synthesis (CTS) ,Routing, Static Timing Analysis (STA), DRC fixing , Physical Verification.Expertise in PPA Enhancement for GPU and CPU Expertise in handling various P&R related issues in Block level design.Expertise in following EDA tools: Fusion Compiler,ICC2, Innovus, Synopsys primetime ,Calibre (Mentor Graphics)

Experience

Cadence

Lead Engineer

Apr 2025Present · 11 mos · Bengaluru, Karnataka, India · On-site

Synopsys inc

2 roles

Staff Research Development Engineer

Jun 2023Apr 2025 · 1 yr 10 mos

Reseach and development engineer

Nov 2021May 2023 · 1 yr 6 mos

Synapse design inc.

3 roles

Senior Physical Design Engineer

Promoted

May 2019Dec 2021 · 2 yrs 7 mos

Project Engineer

Apr 2018Nov 2021 · 3 yrs 7 mos

trainee engineer

May 2017Aug 2017 · 3 mos · Ranchi Area, India

Education

Asansol Engineering College

Bachelor of Technology - BTech — electrical engineering

Jan 2012Jan 2016

raniganj high school

Jan 2005Jan 2011

Stackforce found 20 more professionals with 7nm & Fusion compiler

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