Jun 2022 – Present · 3 yrs 9 mos · Noida, Uttar Pradesh, India

• Worked extensively on the RISC-V architecture, contributing to the development and maintenance of OpenSBI(Open Supervisor Binary Interface), a critical component for bootstrapping RISC-V system
• Developed and maintained Worldmon, a hypervisor mode for RISC-V systems, focusing on secure execution and isolation of virtual environments.
• Engineered a SecureOS kernel handling system security, process isolation, and secure boot mechanisms for safe loading and execution of the Linux kernel.
• Responsible for building Tizen OS packages from ARM-based architecture to RISC-V.