Shravani Kode

Product Engineer

Mumbai, Maharashtra, India2 yrs 4 mos experience

Key Highlights

Recognized with a peer bonus at Google for impactful contributions.
Led a team to develop space technology solutions at IIT Bombay.
Integrated advanced ML algorithms into processor design.

Stackforce AI infers this person is a Semiconductor and Aerospace professional with expertise in digital design and hardware engineering.

Contact

Skills

Core Skills

Digital Design VerificationFormal VerificationMachine LearningSoftware DevelopmentElectronic Circuit DesignCommunication Protocols

Other Skills

ASICBash scriptingC++Computer ArchitectureConvolutional Neural Networks (CNN)Decision-MakingDigital Circuit DesignDigital DesignsEagle PCBGitI2CKiCADLinuxPCB DesignPrinted Circuit Board (PCB) Design

About

I’m Shravani Kode, I have completed my Bachelor's in Electrical Engineering with honors and Minor in AI and Data Science from IIT Bombay. I’m interested in digital hardware design, computer architecture, and how AI and machine learning can be accelerated and optimized on modern hardware. I’ve gained hands-on experience through a hardware engineering internship at Google, where I worked on digital design verification and was recognized with a peer bonus for my contributions. I also led the Communication Subsystem for IIT Bombay’s Student Satellite Program, collaborating with a diverse team to develop space technology solutions. I’m passionate about exploring the intersection of intelligent algorithms and advanced chip design. Always curious and up for a challenge, I enjoy connecting with others who share an enthusiasm for hardware, AI, or just cool tech. Feel free to reach out at shravani.kode@gmail.com!

Experience

Google

Hardware Engineering Intern

May 2024 – Jul 2024 · 2 mos · Bengaluru, Karnataka, India

Enhanced digital design verification through formal methods, earning a peer bonus for impactful contributions
Developed a comprehensive formal testbench in SystemVerilog for FIFO design using advanced testbench
automation scripts, achieving 100% formal core coverage and successfully identifying previously masked bugs
Implemented X-propagation checks using Tcl scripting and automated checks for 14 existing design modules
Formulated and executed test plan to verify Weighted Round Robin Arbiter, ensuring robust functionality

Formal VerificationSystemVerilogTclDigital Design Verification

Harvard university

Research Intern

May 2023 – Dec 2023 · 7 mos

Guide: Prof. Vijay Janapa Reddi, John L. Loeb Associate Professor of Engineering and Applied Sciences, John A. Paulson School of Engineering and Applied Sciences, Harvard University
Integrated CFU-Playground into Arch-Gym, enabling iterative processor improvements and exploration of its extensive design space.
Developed an OpenAI gym environment to facilitate the use of various ML algorithms within Arch-Gym and CFU-Playground.
Gained extensive experience with a large open-source codebase, becoming proficient in Conda environments, Bash scripting, Python modules, Linux, and Git version control

PythonBash scriptingLinuxGitMachine LearningSoftware Development

Student satellite program, iit bombay

2 roles

Communication Subsystem Head

Promoted

Mar 2023 – Nov 2023 · 8 mos

Led an interdisciplinary team of 11 students to develop a quality assured antenna deployment system
Executed a three stage recruitment process involving written test, interview and a mini project to test the
technical skills, practical approach and team work of the applicants; selecting 9 out of 70+ candidates

Communication Subsystem Member

Apr 2022 – Nov 2023 · 1 yr 7 mos

Sanket: The mission aims to develop an indigenous Antenna Deployment System for CubeSat applications, with TRL-8
Designed a PCB for implementation of a specialized testing circuit for an antenna deployment system
Implemented UART, SPI and I2C communication protocols to achieve efficient data transmission
Modelled coaxial cable fed dipole antennae and fine-tuned their dimensions to obtain required S11 plots
Conducted comprehensive analysis of Low Noise Amplifier and made a package for the same on EAGLE
Designed a 4-layer PCB for the amplifier, incorporating RF PCB guidelines and meeting project requirements

PCB DesignUARTSPII2CElectronic Circuit DesignCommunication Protocols