Siddhartha Kasyap M — Software Engineer
• Experience of working on technology nodes 180nm, 22nm, 32nm, 14nm and 10nm. • Expertise in physical design flow from RTL to GDSII • Good amount of exposure in scripting languages such as TCL, PERL and PYTHON • Expertise in implementation of ECOs, both logical and timing, and include with/without base change. • Solid understanding of UPF methodology and expertise in power analysis and debug. • Initial debugging capabilities in areas of IR/RV, formal Verification and DFT. • Experience in methodology and flow development
Stackforce AI infers this person is a VLSI design engineer with expertise in physical design and power analysis.
Location: Bengaluru, Karnataka, India
Experience: 14 yrs 10 mos
Skills
- Physical Design
- Power Analysis
Career Highlights
- Expert in physical design flow from RTL to GDSII.
- Strong background in power analysis and optimization.
- Proficient in multiple scripting languages for automation.
Work Experience
Intel Corporation
Sr. Physical design Engineer (4 yrs 4 mos)
Qualcomm
Staff Engineer (3 yrs 6 mos)
Cadence Design Systems
Lead Application Engineer (1 yr 7 mos)
Intel Corporation
Component Design Engineer (5 yrs 5 mos)
Education
m.tech at National Institute of Technology Calicut
Bachelor of Technology (B.Tech.) at Audisankara college of engineering and technology
