Sanhith Kosuri — Software Engineer

Masters in VLSI with 5 years of experience in VLSI Design and Verification. Expertise in RTL coding, STA, Integration, Verification, Debug Tools, and FPGA Design Flow. Skill Set:- HDL Languages: Verilog, System Verilog, VHDL FPGAs: Xilinx 7-Series, ZYNQ, Ultrascale+, Intel Stratix V, Arria 10, Max 10 Design Tools: Quartus Prime, Vivado HLX, Vivado Vitis, Cadence Virtuoso Verification Tools: QuestaSim, Vivado Simulator, NCSim Timing Tools: TimeQuest Timing Analyzer, Vivado Timing Analyzer, OpenTimer Debug Tools: Signal Tap Analyzer, System Console, ILA, VIO Version Control/ Configuration Management Tools: GIT, Bitbucket, SVN Tortoise, JIRA Protocols/Interface Specifications: PCIe, CCI-P, Avalon, AXI Operating Systems: Linux, Windows Scripts/Languages: TCL, XML, C, C++

Stackforce AI infers this person is a VLSI Design and Verification Engineer with expertise in FPGA technologies.

Location: Bengaluru, Karnataka, India

Experience: 9 yrs