Sanhith Kosuri — Software Engineer
Masters in VLSI with 5 years of experience in VLSI Design and Verification. Expertise in RTL coding, STA, Integration, Verification, Debug Tools, and FPGA Design Flow. Skill Set:- HDL Languages: Verilog, System Verilog, VHDL FPGAs: Xilinx 7-Series, ZYNQ, Ultrascale+, Intel Stratix V, Arria 10, Max 10 Design Tools: Quartus Prime, Vivado HLX, Vivado Vitis, Cadence Virtuoso Verification Tools: QuestaSim, Vivado Simulator, NCSim Timing Tools: TimeQuest Timing Analyzer, Vivado Timing Analyzer, OpenTimer Debug Tools: Signal Tap Analyzer, System Console, ILA, VIO Version Control/ Configuration Management Tools: GIT, Bitbucket, SVN Tortoise, JIRA Protocols/Interface Specifications: PCIe, CCI-P, Avalon, AXI Operating Systems: Linux, Windows Scripts/Languages: TCL, XML, C, C++
Stackforce AI infers this person is a VLSI Design and Verification Engineer with expertise in FPGA technologies.
Location: Bengaluru, Karnataka, India
Experience: 9 yrs
Career Highlights
- Masters in VLSI with 5 years of experience.
- Expertise in RTL coding and FPGA design flow.
- Proficient in multiple HDL languages and design tools.
Work Experience
Juniper Networks
Hardware Engineer 3 (3 yrs 4 mos)
Hardware Engineer 2 (1 yr 11 mos)
Unizen Technologies Pvt Ltd
Senior FPGA Engineer (1 yr 3 mos)
Associate FPGA Engineer (1 yr 11 mos)
Sandeepani School of VLSI Design
Trainee (7 mos)
Education
Dual Degree (B.Tech and M.Tech) at Lovely Professional University
HSC at Sri Chaitanya Junior College
SSC at Bhashyam Public School