MANAVKUMAR KANOJIYA

Software Engineer

Surat, Gujarat, India5 yrs 2 mos experience
Highly Stable

Key Highlights

  • Expert in Functional Verification and UVM methodologies.
  • Proficient in multiple programming and scripting languages.
  • Strong background in Digital Electronics and Circuit Design.
Stackforce AI infers this person is a Digital Electronics Verification Engineer with expertise in ASIC design and verification.

Contact

LinkedIn

Skills

Core Skills

Functional VerificationUniversal Verification Methodology (uvm)

Other Skills

AccountingDebuggingDigital Circuit DesignDigital ElectronicsElectronicsGate Level SimulationKeilLinuxMatlabMicrosoft ExcelMicrosoft OfficeNI MultisimPerlShell ScriptingSystemVerilog

Experience

Qualcomm

Senior Design Verification Engineer

Jun 2024 – Present · 1 yr 9 mos · Bengaluru, Karnataka, India · On-site

Gate Level SimulationTest PlanningFunctional VerificationDebuggingSystemVerilogUniversal Verification Methodology (UVM)

Einfochips (an arrow company)

2 roles

ASIC Verification Engineer

Jan 2021 – Jun 2024 · 3 yrs 5 mos

Gate Level SimulationTest PlanningFunctional VerificationDebuggingSystemVerilogUniversal Verification Methodology (UVM)

ASIC Verification Engineer

Jan 2020 – Dec 2020 · 11 mos

Gate Level SimulationTest PlanningFunctional VerificationDebuggingSystemVerilogUniversal Verification Methodology (UVM)

Education

Nirma University

Bachelor's degree

Jan 2016 – Jan 2020

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