Prashant Kumar

Software Engineer

Noida, Uttar Pradesh, India11 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Analog and Mixed-Signal Circuit Design.
Proven track record in High-Speed IO Design for Automotive.
Strong background in VLSI Design and Verification.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and Analog Circuit Design.

Contact

Skills

Core Skills

Analog Circuit DesignCircuit Design

Other Skills

3V GPIO DesignApache RedhawkCC++CLK & Data Input Buffers DesignCMOSCMOS designCadence EncounterCadence SpectreCadence VirtuosoDebuggingDigital Circuit DesignEM-IREldo ADMSEmbedded Systems

About

I am currently working with the Analog,Mixed-Signal & IO Design group at ST Microelectronics. Previously I have worked with Cypress Semiconductors (Now Infineon Technologies) on the circuit design of 3V/1.8V GPIO/HSIO in 40 nm technology targeted for IOT and Automotive Products supporting multiple protocols (Ethernet,HS-SPI,Hyperbus,eMMC etc.) as well as CLK & Data Buffers in 130 nm technology targeted for ULE FRAM. Apart from circuit design, Complete Verification Checks of relevant blocks including Hi-Z/DC Path/Floating Nodes(using Finesim), Static ERC, SOA, APL View Generation, Monte-Carlo simulations, EMIR & Reliability Analysis, IO characterization (.lib generation) & On-Chip Variability(OCV) analysis were performed. I have completed my M.Tech in VLSI Design,Tools & Technology(VDTT) from IIT Delhi sponsored by Cypress Semiconductors. I am among the branch toppers in B.E (Electronics & Communication Engineering) from Delhi College of Engineering, New Delhi. In my undergraduate studies i have worked on projects related to digital design. Reach out to me if you want to talk of VLSI design or cricket.

Experience

Stmicroelectronics

2 roles

Staff Engineer

Apr 2025 – Present · 11 mos · Noida, Uttar Pradesh, India

Technical Leader

Oct 2022 – Mar 2025 · 2 yrs 5 mos · Noida, Uttar Pradesh, India

Ministry of railways, government of india

Assistant Signal & Telecom Engineer(ASTE)/Indian Railway Service of Signal Engineers(IRSSE)

Jul 2019 – Oct 2022 · 3 yrs 3 mos · Secunderābād, Telangana, India

Deployment and Maintenance of Signaling and Telecom Infrastructure of Indian Railways

Cypress semiconductor corporation

4 roles

Senior Design Engineer

May 2018 – Jul 2019 · 1 yr 2 mos · Bengaluru Area, India

 3V GPIO Design (Fmax = 80 MHz) in 40 nm targeted for IOT Purpose
o Design of configurable Output Path Supporting (8mA-1mA) drive strength @ (HV=1.65V-3.63V) in fast & slow mode and staggered Pre-Driver with slew-rate control for SSO Noise optimization
o Design of Input Path (LV= 0.99V-1.26V) with CMOS/Automotive/TTL compliance. Multiple flavors of Level Shifter designed for Control Circuitry and Data Path
o SSO(Simultaneous Switching Outputs) Noise analysis for multiple Inductance & IOs combinations
 1.8V High Speed IO(HSIO) Design ( Fmax = 200 MHz) in 40 nm Technology
o Design of Output Data Path Level Shifter
o Design of CMOS Mode Clock Input Buffer with Hysteresis
 Other Related Blocks for above Projects
o Power Detector, AMUXT, Basics of ESD Concepts

3V GPIO DesignHigh Speed IO DesignNoise analysisLevel Shifter designCMOS designAnalog Circuit Design+1

Design Engineer

Jul 2016 – Apr 2018 · 1 yr 9 mos · Bengaluru Area, India

 3V High Speed IO(HSIO) Design (Fmax = 133 MHz) with 5V GPIO Support in 40 nm targeted for Automotive purpose
o Design of Output Data Path Level Shifter
o Design of Input Buffer for (Ethernet/HS-SPI/Hyperbus) @(HV=3V) along with GPIO Support (CMOS/AUTO/TTL,100 MHz) support @(HV=5V)
 CLK & Data Input Buffers Design(Fmax = 108 MHz) in 130 nm targeted for Ultra Low Energy(ULE) FRAM
o 1.8V/3V range operation using a voltage select bit and SSO Noise Analysis
 Design of Power Switch with 25 mA current drive and certain slew-rate(slow VDD Ramp-Up) for EFUSE block in 40 nm technology node to meet power sequencing and supply ramp rate requirements for read/write operation
 Complete Verification Checks of relevant blocks including Hi-Z/DC Path/Floating Nodes(using Finesim), Static ERC, SOA, APL View Generation, Monte-Carlo simulations, EMIR & Reliability Analysis
 IO characterization (.lib generation,post-processing,Quality Checks) using Synopsys Liberty NCX & On-Chip Variability(OCV) Analysis

High Speed IO DesignCLK & Data Input Buffers DesignVerification ChecksIO characterizationAnalog Circuit DesignCircuit Design

Co-op Masters

Jan 2016 – May 2016 · 4 mos · Bengaluru Area, India

Worked on the design of 200 MHz high speed,low power Dual Data Rate(DDR) input-output(IO) Buffer in UMC LL65(65 nm) technology node as a part of my M.tech Thesis.
 Worked on the design of inverter-based and comparator-based input buffers with trip point control, leakage control and high-speed operation capability
 Designed output buffer with new high speed,low power level shifter architecture having minimal contention between pull-up and pull-down paths for high speed requirements

Co-op Masters

May 2015 – Jul 2015 · 2 mos · Bengaluru Area, India

Worked on the design of Differential input buffer based on Low Voltage Differential Signalling(LVDS) IO standard in s8atlasana 130 nm technology node

Indian institute of technology, delhi

Project Assistant

Jul 2014 – Jun 2016 · 1 yr 11 mos · New Delhi Area, India

M.tech(VLSI Design,Tools & Technology) Sponsored by Cypress Semiconductors

Synopsys inc

Intern(technical)

Aug 2013 – Jan 2014 · 5 mos · Noida Area, India

 Studied memory architecture using pre-decoding and column muxing approach
 Performed Analysis of TS16 (TSMC 16 nm) GL (Generic Leakage),LL (Low Leakage) Bit-cells (hd,hc,hp) for various margins (e.g. read margin ,DC write margin, Static Noise Margin(SNM), read current, leakage current etc.) using SYNOPSYS PIPE plug-in
 Studied write-assist circuitry using Negative Bit-line approach to ensure Bit-cell Write happens across all PVT corners