Ranjith das

Software Engineer

Bengaluru, Karnataka, India11 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in SOC timing integration and sign-off.
Proven experience in EDA and production industries.
Strong background in power analysis and static timing analysis.

Stackforce AI infers this person is a VLSI and EDA expert with a focus on timing and power analysis.

Contact

Skills

Core Skills

Static Timing AnalysisPower Analysis

Other Skills

VLSIDigital Circuit DesignAnalog Circuit DesignCadence VirtuosoMatlabVHDLSignal Processing

About

Have proficiency in SOC timing integration and sign-off. Have working experience both in EDA as Application Engineering as well as in Production industry as Timing sign-off lead.

Experience

11 yrs 7 mos

Total Experience

2 yrs 8 mos

Average Tenure

4 yrs 7 mos

Current Experience

Cadence system design and analysis

Principal Application Engineer

Jul 2024 – Present · 1 yr 9 mos · Bengaluru, Karnataka, India

Intel corporation

SoC Design Engineer

Sep 2021 – Present · 4 yrs 7 mos · Karnataka, India · On-site

Timing Sign off tools and methodology development and sign-off support for Timing integration and sign-off

Power AnalysisStatic Timing Analysis

Synopsys inc

Application Engineer

Sep 2018 – Sep 2021 · 3 yrs · Karnataka, India · On-site

Primetime and Prime power Application Engineer. Design consultant for Timing and Power Sign off

Power AnalysisStatic Timing Analysis

Intel corporation

2 roles

Graphics Hardware Engineer

May 2015 – Jun 2017 · 2 yrs 1 mo · Bengaluru Area, India

STA ( Static timing Analysis) & power Sign-off

Graduate Technical Intern

Jun 2014 – May 2015 · 11 mos · Bengaluru Area, India

ADVANCED WIRELESS BATTERY CHARGER:

National aerospace labs

Junior Research Fellow

Jun 2012 – Jun 2013 · 1 yr

Implemented several signal processing Papers which includes implementation of LMS filters, Lattice filters, Hilbert Huang Transform, RLS filters, FIR and IIR filters