Jay Maradia

Software Engineer

Ahmedabad, Gujarat, India7 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in UVM and SystemVerilog for verification.
  • Strong background in debugging and scripting.
  • B.Tech in Electronics and Communication Engineering.
Stackforce AI infers this person is a Verification Engineer in the IT and services industry.

Contact

LinkedIn

Skills

Core Skills

Universal Verification Methodology (uvm)Systemverilog

Other Skills

DebuggingLinuxScripting

About

Experienced Engineer with a demonstrated history of working in the information technology and services industry. Skilled in Debugging, Linux, Scripting, Universal Verification Methodology (UVM), and SystemVerilog. Strong engineering professional with a B. Tech focused in Electronics and Communication Engineering from Ganpat University.

Experience

Einfochips (an arrow company)

2 roles

Senior Verification Engineer

Promoted

Jun 2021 – Present · 4 yrs 9 mos

Universal Verification Methodology (UVM)SystemVerilogDebuggingScriptingLinux

ASIC Verification Engineer

Aug 2018 – Aug 2021 · 3 yrs

Universal Verification Methodology (UVM)SystemVerilogDebuggingScriptingLinux

Education

Ganpat University

B. Tech — Electronics and Communication Engineering

Jan 2015 – Jan 2018

Nirma University

Diploma — Electronics and Communication Engineering

Jan 2011 – Jan 2015

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