Rohan Pachange

Software Engineer

Hyderabad, Telangana, India6 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expertise in advanced semiconductor technologies from 22nm to 5nm.
Proven track record in enabling engineers through technical training.
Strong background in physical design and layout verification.

Stackforce AI infers this person is a Semiconductor Engineering expert with a focus on advanced physical design technologies.

Contact

Skills

Core Skills

Semiconductor EngineeringPhysical DesignTechnical TrainingProgram ManagementLayout Verification

Other Skills

22/14/10/7/5 nm nodeAnalog SemiconductorsCC++Clock Tree SynthesisCommunicationCustom layoutDRAMDesign Rule Checking (DRC)DevelopmentDynamic Random-Access Memory (DRAM)EDAElectronicsEngineeringFloorplanning

About

A creative and dedicated Physical Design Engineer with several years of experience in both technology development and product manufacturing in the industry. I am passionate about digital/analog ASIC design, having worked on IP level designs for a multitude of devices in different domains. I have worked on multiple nodes ranging from 22nm to 5nm with an interest in working towards new technologies. My career goal is to work for leading companies with excellent team members who drive engineering and technological innovations. Looking forward to contribute towards growing these teams and building them into larger successful organizations that can serve the global market

Experience

Micron technology

2 roles

Senior Engineer

Promoted

Nov 2025 – Present · 4 mos · Hyderabad, Telangana, India

Part of TPG-Technology and Product Group, enabling engineers on new age Memory Technology both Design and Process. Experienced in DRAM, NAND and HBM Design, Development and Packaging.

DRAMNANDHBM DesignDevelopmentPackagingSemiconductor Engineering+1

Engineer

Jan 2022 – Present · 4 yrs 2 mos · Hyderabad, Telangana, India

Part of TPG-Technology and Product Group, responsible for Technical Content Creation and Management for new as well as experienced engineers. Key focus is on DRAM, NAND and HBM products engineer enablement. Various Program Management within Business group.

Technical Content CreationManagementDRAMNANDHBMTechnical Training+1

Intel corporation

Layout Verification Engineer

Apr 2019 – Dec 2021 · 2 yrs 8 mos · Banglore

Responsible for delivering tape-out ready designs with PV convergence. Worked on 22/14/10/7/5 nm node for post synthesis pioneering and PV convergence at section/super-section hierarchy.

Tape-out ready designsPV convergence22/14/10/7/5 nm nodePhysical DesignLayout Verification