Sahil Chawla

Operations Associate

Gurugram, Haryana, India9 yrs 6 mos experience
Highly Stable

Key Highlights

  • Expert in low-latency trading systems development.
  • Strong background in event-driven engines for market data.
  • Proven track record in optimizing performance for high-frequency trading.
Stackforce AI infers this person is a Fintech expert with strong expertise in low-latency systems and wireless technologies.

Contact

Skills

Core Skills

Low LatencyHigh-frequency TradingC++AlgorithmsWireless TechnologiesPython

Other Skills

AnsibleChoreographyData StructuresEagle PCBEmbedded SystemsEngineeringEvent PlanningExchange ConnectivityFilm DirectionMATLABMicrosoft OfficeMicrosoft PowerPointMicrosoft WordModern DanceMusic Videos

About

Sahil is a senior C++ engineer with end-to-end experience building trading systems across China, UK, and Indian markets. He has a strong background in event-driven engines for market data, order entry, risk, and simulations. At Mathisys, he has developed expertise in designing low-latency software using advanced concurrency primitives, kernel-bypass and hardware-assisted networking, IPC, and rigorous micro-bench-marking and profiling. Prior to this, he worked at Qualcomm developing software reference models for next-generation Wi-Fi chip-sets.

Experience

Mathisys advisors

Infrastructure Specialist

Jan 2023Present · 3 yrs 2 mos · Gurugram, Haryana, India · On-site

  • + Low latency high frequency trading systems development
  • + Developed and optimized event driven real time systems with high throughput and performance
  • + Integrated multiple global exchanges
  • + Experience in developing multi-threaded applications with different IPCs (user space sockets, shared memory) for synchronization
Low LatencyExchange ConnectivityHigh-Frequency TradingC++AlgorithmsResearch+4

Qualcomm

2 roles

Senior Engineer

Promoted

Nov 2021Jan 2023 · 1 yr 2 mos

  • + Feature owner of Wi-Fi Round Trip Time (RTT/11az) hardware block used in indoor positioning of smartphones
  • + Suggested a 20% memory compression technique for buffers used in IFFT block with negligible degradation in performance
  • + Refactoring model code to reduce simulation time and size by utilizing the concepts of code re-use in various design patterns
MATLABC++AlgorithmsData StructuresEngineering

Engineer

Jul 2019Oct 2021 · 2 yrs 3 mos

  • + Developed a new reception mode to support transmitter beamforming on narrow band users based on the latest IEEE 802.11be standard
  • + Implemented a correlation-based fixed-point algorithm for early bandwidth detection to obtain gain using frequency diversity
  • + Delivered High-Level Synthesis radio model implemented using SystemC for an Internet of Things Wi-Fi and Bluetooth chipset
  • + Proposed optimized thresholds for the bandwidth detection algorithm using false alarm analysis in the presence of interference
C++AlgorithmsData StructuresEngineeringWireless TechnologiesEmbedded Systems

Indian institute of technology, bombay

7 roles

Teaching Assistant

Jul 2018Apr 2019 · 9 mos

  • Teaching assistant for the following two courses:
  • 1. Neuromorphic Engineering (2018)
  • 2. Digital Communications (2019)
  • Awarded - Excellence in Teaching (2018)

Annual InSync Dance Showcase - Overall Coordinator

May 2017Apr 2018 · 11 mos

  • 1. Nominated to manage INR 2.5 lakhs and lead a team of 180 dancers for executing annual dance flagship event
  • 2. Partnered with Kala Ghoda Arts Festival to provide national-level launch-pad to Indian Folk Dance performance
  • 3. Fostered the social cause of underprivileged children by providing a stage targeting an outreach of 10k+ students
  • 4. Upturned 40% budget deficit by optimization and reduction of publicity costs through revamping digital publicity
  • 5. Diversified existing publicity through creative avenues resulting in 80% y-o-y increase in overall participation

Student Mentor

Apr 2017Apr 2019 · 2 yrs

  • 1. Selected 1 amongst 92 from 290 applicants based on peer reviews, all-around achievements and mentoring skills
  • 2. Facilitated smooth transition of 12 freshmen to life at IIT by supporting their academic and co-curricular pursuits
  • 3. Mentored for 2 consecutive years to help enhance the academic performance through semester-wide planning
  • 4. Counselled 14 department juniors on one-to-one basis to cope up with academic pressure

Visible Light Communication Link (using LEDs)

Jan 2017Apr 2017 · 3 mos

  • Course - Electronics Design Lab
  • 1. Built a wireless optical link for data transmission at 100 kbps with zero error rate at a distance of 1m
  • 2. Devised a protocol to send information and clock synchronization bits over the link
  • 3. Designed clock recovery circuit using a phase locked loop for synchronous data transfer

Microprocessor Design and Testing

Oct 2016Nov 2016 · 1 mo

  • Course - Microprocessors
  • Instructor - Prof. Virendra Singh (Electrical Engineering, IIT Bombay)
  • 1. Designed and simulated a 6-stage 16-bit pipelined processor and a multi-cycle RISC processor in VHDL
  • 2. Implemented the multi-cycle RISC processor(with optimized performance and hazard detection techniques) on Cyclone IV E FPGA

Teaching Assistant

May 2016Apr 2017 · 11 mos

  • Teaching assistant for 3 different courses.
  • 1. EE 101 (Introduction to Electrical and Electronics Circuits) under the guidance of Prof. B.G Fernandes. This course ran in summers 2016 (May - June 2016)
  • 2. EE 101 (Introduction to Electrical and Electronics Circuits) under the guidance of Prof. Subhananda Chakrabarti. This course was running in autumn semester (July - November 2016)
  • 3. EE 112 (Introduction to Electronics) under the guidance of Prof. Subhananda Chakrabarti. This course was running in spring semester (Jan - Apr 2017)
  • Duties:
  • a. Conducted Weekly tutorials and informal discussion sessions of over 100 registered students
  • b. Also provided assistance in preparing quizzes, mid-semester and end-semester question papers and grading answer scripts

Undergraduate Research Assistant

May 2016Jul 2016 · 2 mos

  • Designing Controller for Wire-EDM | Summer UnderGraduate Research Project
  • Part of 5 member team with guide - Prof. S.V Kulkarni, Department of Electrical Engineering, IIT Bombay
  • Scope: Optimizing slicing process by Wire–EDM to develop silicon wafers that increase the efficiency of PV cells
  • 1.Comparative study of conventional methods (Inner Diameter Saw, Abrasive multi-wire saw) of silicon ingot slicing with Wire – EDM analysing Kerf Loss, Slicing Rate, Material Removal Rate and Surface Integrity
  • 2.Experimental investigation on silicon/steel ingots to understand the mechanism & potential of Wire – EDM
  • 3.Proposed a MATLAB Simulation model of the electric discharge generated during cutting process of workpiece
  • 4.Designed the typical Power Electronic Circuitry to generate pulse train without load using Diptrace

Inter iit cultural meet

Dance Captain

Jul 2017Feb 2019 · 1 yr 7 mos

  • 1. Lead a team of 70+ dancers for 6 competitions over the span of 2 years
  • 2. The team achieved the following:
  • a. 1st position in group dance competition, 2017 - Gold Medal
  • b. 1st position in duet dance competition, 2017 - Gold Medal
  • c. 2nd position in street battles, 2017 - Silver Medal
  • d. 1st position in duet dance competition, 2018 - Gold Medal
  • e. 1st position in street battles, 2018 - Gold Medal
  • f. 2nd position in group dance competition, 2018 - Silver Medal
  • 3. Overall Dance Champions for two consecutive years
  • 4. Overall Champions for the year 2018

Qualcomm

Summer Internship

May 2017Jul 2017 · 2 mos · Greater Hyderabad Area

  • Qualcomm India Private Limited, Hyderabad
  • Role - System Developer
  • Highlight - Received PPO (Pre-Placement Offer) for joining as full time employee in 2018
  • 1. Enhanced the debugging capabilities of poky (reference distribution provided by Yocto Project) and Qualcomm distribution for the Snapdragon 625 processor
  • 2. Enabled on target and remote debugging by explicitly scripting new recipes to install 'gdbserver' package on the Linux image for Snapdragon 625 and establishing cross development environment for debugging at the host
  • 3. Analyzing the chain of package dependency in poky and Linux image for Snapdragon 625. Provided an exclusive list of upstream recipes and internal recipes. Using python generated files that illustrated the run-time and build-time dependencies of all the packages installed on the image. Identified the redundant packages in the image using the files generated
  • 4. Proposed to build hardware emulators for Qualcomm processor chips that will improve the development process in the company

Education

Indian Institute of Technology, Bombay

Master of Technology - MTech + Bachelor of Technology - BTech — Electrical Engineering.

Jan 2014Jan 2019

R.S.D. Raj Rattan Public School

Senior Secondary

Jan 2012Jan 2014

St. Joseph's Convent School

Matriculation

Jan 1999Jan 2012

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