Adwait Gupte

Software Engineer

New York, New York, United States17 yrs 6 mos experience
Highly Stable

Key Highlights

  • Expert in building low-latency trading systems.
  • Proficient in FPGA development for high-frequency trading.
  • Strong background in Equities Market Making.
Stackforce AI infers this person is a Fintech expert specializing in high-frequency trading systems and FPGA development.

Contact

Skills

Other Skills

AlteraCC++Deep Packet InspectionFIXFPGAHigh Frequency TradingJavaLow LatencyRTL codingSERDESVHDLVerilogXilinx

About

Computer Engineer with extensive experience building systems for High Frequency Trading

Experience

3red partners

Senior Engineer

Sep 2025Present · 6 mos

Goldman sachs

2 roles

Non-compete

Mar 2025Sep 2025 · 6 mos

Vice President

May 2019Mar 2025 · 5 yrs 10 mos

  • Equities Market Making

Tower research capital

Engineer

Nov 2017May 2019 · 1 yr 6 mos · New York, New York

  • Building HFT systems targeting extremely low latencies.

The d. e. shaw group

Engineer

Jun 2014Nov 2017 · 3 yrs 5 mos · Greater New York City Area

  • Built trading system for HFT in Futures

Vss monitoring

2 roles

Product Manager

Jan 2014Jun 2014 · 5 mos · San Francisco Bay Area

  • Defining product strategy for the Big Data Visibility initiative within VSS Monitoring
  • Defining/prioritizing feature for development
  • Identifying technology partnerships that align with product strategy
  • Working with technology partners to define and build prototypes for joint solutions

Sr. FPGA Engineer

Jun 2012Jan 2014 · 1 yr 7 mos · San Francisco Bay Area

  • Worked on packet processing FPGAs handling data at line rate on 10G and 1G links
  • Worked on TCP offload engine
  • Worked on FPGAs handling GTPv1 and GTPv2 traffic

Algo-logic systems

2 roles

Design Engineer/Member of Technical Staff

Aug 2010Jun 2012 · 1 yr 10 mos · San Francisco Bay Area

  • Development lead for FPGA projects dealing with processing of market/order data.
  • All the projects target the minimum possible theoretical latency for latency sensitive DMA customers.
  • Deep Packet Inspection of large volumes of data to check for compliance with business rules.

Design Engineer

Feb 2010Aug 2010 · 6 mos · San Francisco Bay Area

  • Worked on FPGA solutions for processing market/order data to achieve the lowest possible theoretical latencies for latency sensitive DMA customers.

Iowa state university

2 roles

Graduate Research Assistant

Jan 2009Feb 2010 · 1 yr 1 mo

  • I worked on interesting research projects using FPGAs which resulted in 3 publications. The work allowed me to gain experience using the Xilinx FPGA toolchain and RTL development in general. It also helped me develop my problem solving skills from identifying and defining a problem to coming up with and evaluating a viable solution.

Teaching Assistant

Aug 2008Dec 2008 · 4 mos

  • Introductory course on C programming. Helped me develop public speaking skills and also helped me brush up the finer details of programming in C.

Education

Iowa State University

MS — Computer Engineering

Jan 2008Jan 2011

University of Mumbai

BE — Information Technology

Jan 2004Jan 2008

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