Neeraj Dwivedi

Software Engineer

Bengaluru, Karnataka, India13 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in end-to-end VLSI power optimization.
Proficient in low power methodologies and ECO techniques.
Experienced in leading power analysis for major semiconductor companies.

Stackforce AI infers this person is a Semiconductor Power Optimization Specialist with extensive experience in EDA tools.

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Skills

Core Skills

Power OptimizationThermal AnalysisGpu Power ManagementEco TechniquesLow Power DesignSoftware Development

Other Skills

AI/ML techniquesAgile MethodologiesAlgorithmsAutomationBashBenchmark vector analysisCC++CerebrusDSO.aiDVFSData StructuresECOEM/IR analysisFunctional specifications

About

Self driven low power engineer. Loop me in if you have something in relation to - ** End to end VLSI Power optimization/analysis/target setting. ** Designing of Software Engineering ** Core-architecture, DS/Algorithms ** Design/EDA : Power analysis and optimization / reduction ** Low Power methodologies, ECO optimization or Timing analysis (STA) ** IEEE UPF 2.1/3.0 Tools - Synopsys PrimePower PTPX, Ansys Power Artist, PPRTL, RTL-A, Cadence Joules, Mentor's PowerPro, VCS, VCLP, Fusion Compiler, DSO, Cerebrus, Empower, Low-power tools, PrimeEco, etc. Believer of having real life hobbies, interests and building a happy and positive culture at workplace.

Experience

13 yrs 2 mos

Total Experience

2 yrs 7 mos

Average Tenure

3 yrs 7 mos

Current Experience

Amd

Senior Staff Engineer

Sep 2022 – Present · 3 yrs 7 mos · Bengaluru, Karnataka, India · On-site

End to end CPU cores Power lead (RTL to Signoff PD). Own the simulation from getting the vectors to budgeting power and driving to PD Power goals. Thermal analysis to check energy centric hotspots in the design/floorplan to power analysis/optimization in meeting signoff goals.
Expertise in benchmark vector analysis. Multibit/ Clock/Power gating/ Vt cell enablement/ Saif Optimization/ and Eco/ Vt-Swap/downsizing for leakage recovery.

Power analysisPower optimizationThermal analysisBenchmark vector analysisPower OptimizationThermal Analysis

Intel corporation

GPU Power Lead

May 2021 – Sep 2022 · 1 yr 4 mos · Bengaluru, Karnataka, India · On-site

Responsible for setting of card model Power targets along with benchmarking and budgeting.
Driving initiatives to reduce/optimize power at different subsystem level ranging from traditional
techniques to new AI/ML techniques for achieving target.
Skills: GPU Power budgeting, target, analysis and optimization – Ponte Vecchio and Rialto [Low-power/ optimization]

GPU Power budgetingPower analysisAI/ML techniquesPower OptimizationGPU Power Management

Synopsys inc

Senior Research And Development Engineer

May 2018 – May 2021 · 3 yrs · Bengaluru, Karnataka, India

Working on core PrimeTime architecture along with prior PrimeEco experience. Developed version-independent flow for PrimeTime to be used across multiple releases. Explored DRC, Power, EM cell and IR drop optimization being part of ECO team.

PrimeTime architecturePower optimizationECO techniquesPower OptimizationECO Techniques

Qualcomm

Senior Engineer

Jun 2016 – May 2018 · 1 yr 11 mos · Bengaluru, Karnataka, India

Worked on development of PIE (Power Intent Engine), which is an in-house engine developed to capture Design Power intent specification targeted across design levels (Block/HM, subsystem and top level), design phases (front end simulation/ synthesis and physical design) and tools (VCS, MTI, DC, ICC, CLP, PTPX and LEC). Developed to be in sync with latest CPF and UPF (UPF 2.0/2.1) versions.
Worked on multiple technology nodes including 10lp and 7ff w.r.t Power analysis and reduction
which lead multiple SOCs, core and IPs to save considerable amount of power by doing
sequential, architectural & micro-architectural level changes.
Skills: Perl/Python, Library, CPF, UPF 2.0/2.1/3.0, Power analysis and Power optimization.

Power Intent EnginePower analysisLow Power MethodologiesPower OptimizationLow Power Design

Mentor graphics

2 roles

Senior Member Of Technical Staff

Promoted

Dec 2014 – Jan 2016 · 1 yr 1 mo · Noida, Uttar Pradesh, India

Responsible for coming up with functional and implementation specifications for the power optimization related projects. Doing hands on coding in OOPs along with writing test-plans and unit-testing via tcl, hdl.
Debugged and resolved multiple critical / blocker bugs for customer.

Functional specificationsOOPsTCLPower OptimizationSoftware Development

Research And Development Engineer

Aug 2012 – Nov 2014 · 2 yrs 3 mos · Noida, Uttar Pradesh, India

Part of the backend R&D team responsible for developing new techniques for reducing power in RTL designs for their product PowerPro CG and PowerPro MG.
Skills: C++, TCL, Verilog, VHDL, Low Power Methodologies at RTL level.

Low Power MethodologiesC++TCLLow Power DesignSoftware Development