kalyan kota

Software Engineer

Bengaluru, Karnataka, India9 yrs 9 mos experience

Highly Stable

Key Highlights

Expert in Analog and RFIC Design with M.Tech from IIT Delhi.
Designed multiple high-performance RF components including VCOs and LDOs.
Proficient in Cadence tools for IC design and simulation.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Analog and RFIC technologies.

Contact

Skills

Core Skills

Analog Circuit DesignIntegrated Circuit Design

Other Skills

3D-EMAnalog Integrated Circuit DesignCCadence Layout XLCadence RCCadence VirtuosoCircuit DesignElectronicsEncounterIntegrated Circuits (IC)LaTeXLayout DesignLinuxLow-Noise Amplifier (LNA)Matlab

About

My M.Tech at IIT Delhi is primarily concentrated on Analog and RFIC Design.During this period, I have Fabricated Ultra-low power and Novel Band Gap References,designed Opamp's, and Dynamic Latched Comparators, Sigma Delta and Cyclic ADC'S, RF Rceiver Chain (LNA's, Active and Passive Mixer's, VCO) in TSMC, UMC and CIS Technologies. Modelling of Wire-bond Packages were done as a part of y M.Tech Thesis.

Experience

Sitime

Senior Analog Design Engineer

Dec 2023 – Present · 2 yrs 3 mos · Bengaluru, Karnataka, India · On-site

Aura semiconductor

3 roles

Member of Technical Staff

Feb 2022 – Dec 2023 · 1 yr 10 mos

Voltage Mode Output Drivers and Open Loop Fraction Dividers

Senior Analog Design Engineer

Promoted

Feb 2019 – Feb 2022 · 3 yrs

High-performance RF Designs such as VCOs and Output Drivers combined with lab evaluation and IBIS Modelling

Analog Design Engineer

Jun 2016 – Feb 2019 · 2 yrs 8 mos

Band Gaps, LDO, High-Speed RF Dividers, and Output Drivers

Cadence design systems

Internship

May 2015 – Jun 2015 · 1 mo · Noida

Description:
Designed Schematic and layout of S-band LNA
Designed Double balanced Mixer and VCO including Layouts in gpdk 180nm Technology
Designed a Temperature and Supply insensitive Voltage reference (BGR) in gpdk 90nm technology
Designed Low Dropout Regulator (LDO) to isolate VCO & LNA supply from BGR generator.
Integrated the entire Receiver with BGR using MTS (Multi Technology Simulation) in Virtuoso Schematic XL
Achievements:
LNA (Gain ~12dB,NF ~3dB)
Mixer(Conversion gain ~13dB,NF ~10dB ,1dB compression point ~ -4dB ,Input IP3=6 dB , Input IP2=30 dB)
VCO (4 bit , 2-3 Ghz, phase noise -100dBc/Hz @1MHz offset)
BGR(<1mV Variation w.r.t variation in Process, 15% Variation in Supply and -20 to 1000 temperature)
Integrated Receiver (Gain ~27dB ,NF ~6dB)