Abir Chakraborty

CTO

San Francisco, California, United States13 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in compiler design and hardware emulation.
  • Proven experience in developing parallel computing solutions.
  • Strong background in semiconductor industry technologies.
Stackforce AI infers this person is a Semiconductor Engineering Expert with a focus on Compiler Design and Hardware Emulation.

Contact

LinkedIn

Skills

Core Skills

Compiler DesignHardware Design

Other Skills

Algorithm DesignAlgorithmsAngularJSCC++Compiler InfrastructureCore JavaData StructuresDebuggingDesign PatternsEDAHardware EmulationLinuxNode.jsOOP

Experience

Synopsys inc

R&D Engineering, Architect

Nov 2024 – Present · 1 yr 4 mos

Cadence design systems

Software Architect

May 2022 – Nov 2024 · 2 yrs 6 mos · San Jose, California, United States

Cerebras systems

Member Of Technical Staff

Mar 2021 – Apr 2022 · 1 yr 1 mo

Synopsys inc

3 roles

Sr R&D Engineer-II

Jun 2018 – Mar 2021 · 2 yrs 9 mos

  • Compiler infrastructure for next generation highly parallelized compiler for Zebu emulator.

Senior R&D Engineer

Promoted

May 2016 – Jun 2018 · 2 yrs 1 mo

  • UPF compiler for hardware accelerated emulation, Power Aware emulation.
  • Bringup of large designs from top chipmakers.

R&D Engineer-II

Jun 2012 – May 2016 · 3 yrs 11 mos

Education

Jadavpur University

Bachelor of Engineering (B.E.) — Computer Science

Jan 2008 – Jan 2012

Patha Bhavan

Jan 1996 – Jan 2008

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