Vidya S — Software Engineer
I have 2+ years of working experience in Physical Synthesis in cutting-edge technology nodes (3nm, 4nm and 6nm) with TSMC fabrication foundries. Presently working as Physical Synthesis Engineer (Backend) in the Camera Image System Processor ISP division at MediaTek Bengaluru. Responsible for Physical Synthesis and implementation and Quality checks like LEC (conformal), ATPG pattern generation and coverage analysis, and pre-STA check for mobile SOCs chipset. From this work experience gained knowledge and understanding of the entire flow of digital IC design and provided optimal solutions to fix congestion and critical timing issues in the design. I am an M.tech graduate in the field of VLSI Design and Embedded Systems and also trained in DFT (Design for testability) from ChipEdge.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Synthesis and Digital IC design.
Location: Bengaluru, Karnataka, India
Experience: 5 yrs 2 mos
Skills
- Synthesis
- Automatic Test Pattern Generation (atpg)
Career Highlights
- 2+ years in Physical Synthesis at TSMC technology nodes
- Expertise in quality checks and timing issue resolution
- M.Tech in VLSI Design with DFT training
Work Experience
MediaTek
Synthesis Engineer (On Contract) (3 yrs 8 mos)
Bapuji Institute of Engineering & Technology, DAVANAGERE
Assistant Professor (1 yr 6 mos)
Education
Master of Technology - MTech at Siddaganga Institute Of Technology
Bachelor of Technology - BTech at Electronics and Instrumentation-UBDT
