Abhirup Lahiri

Product Manager

Bengaluru, Karnataka, India16 yrs 9 mos experience

Highly Stable

Key Highlights

Inventor of 20 US patents with 18 granted.
Over 16 years of experience in analog and RF IC design.
Expertise in high-frequency circuit design and DSP algorithms.

Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in Analog and RF circuit design.

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Skills

Core Skills

Analog Circuit DesignPllRf

Other Skills

ADPLLASICApplication-Specific Integrated Circuits (ASIC)CCMOSCadence VirtuosoCircuit DesignContinous Time Delta Sigma ADCDACsDCODLFDSP algorithmsEDAEthernetFLL

About

Strive to create the state-of-the-art analog, mixed signal and RF ICs. Proven track record to create innovative circuits with best PPA. Expertise in clock generation circuits, designed very wide range of analog circuits and systems. These include crystal oscillator, RC oscillator, LC-VCO, charge-pump PLL, ADPLL (TDC, DCO), CDR (analog, digital), DLL, Phase-interpolator, temperature sensor, baseband circuits for RF receivers like analog filters, analog VGAs, Rx Front end for Bluetooth LE (LNA, Mixer, complex IF filter), phase-shifters (ppf), band-gap reference, LDO, HDO, asynchronous digital LDO, buck converter, low distortion amplifiers, Continous Time Delta Sigma Modulator (CT-DSM), Asynchronous SAR ADC, Analog Front-End interface for magnetic sensor, clock duty cycle corrector, frequency doublers, GHz RF-DACs, DTC, phase interpolators, high linearity and high bandwidth ADC input drivers and sampling networks, injection locked and multi-phase clock generation circuits. Inventor of 20US Patents (18 granted) and first author of several papers in IEEE Solid State Circuits journals and conferences: JSSC, CICC, ESSCIRC. Over 16 years of design experience while working as an individual contributor, team leader and manager in European, American semiconductor companies in Switzerland, Ireland, France and India.

Experience

Marvell technology

Principal Engineer

Jan 2024 – Present · 2 yrs 2 mos · Bangalore Urban, Karnataka, India · On-site

Worked on wireline transceivers.
1. Sub-blocks of LC PLL and clocking for the transceiver supporting PCI protocols (Gen5-1).
2. Design of 12 GHz ADPLL for Custom D2D: TDC, DLF, DCO, regulators, bgr and PLL top VT budgeting.
3. Built innovative DSP algorithms to improve link BER by orders of magnitude. Silicon verified proof of concept demonstrated for 224Gsps Ethernet link, two Patents filed.
Now architecting very low jitter receiver clocking (PLL, distribution, CDR) for 425Gsps PAM6-8 Ethernet links. Also, working with teams in US, Canada on DSP.

wireline transceiversLC PLLclockingADPLLDSP algorithmsAnalog Circuit Design+1

Xilinx

3 roles

Analog/RF Design Manager

Feb 2023 – Dec 2023 · 10 mos

Remotely from Bangalore, I worked and managed a team of engineers based in Dublin (part of Xilinx/AMD Wireless Group), working on state-of-the-art data converter design. Designed very high bandwidth high linearity input networks for TI-ADCs meant for both wireless and instrumentation applications.

data converter designhigh bandwidthhigh linearity input networksAnalog Circuit DesignRF

Staff Engineer

Feb 2022 – Jan 2023 · 11 mos

Part of Xilinx/AMD Wireless Group and working on direct RF ADC and DACs in latest technology nodes.

direct RF ADCDACslatest technology nodesAnalog Circuit DesignRF

Staff Engineer

Oct 2019 – Jan 2023 · 3 yrs 3 mos

Working in Xilinx (now part of AMD) Wireless Group in RF Data Converters Team
1. Worked on RF DAC for transmitters. Has led to 3 Granted US patents on distortion improvement techniques.
2. Designed duty cycle corrector and clock frequency doubler in 16nm Finfet.
3. Designed very high resolution TDC, DTC, high speed comparator in 7nm finfet for timing error detection.
4. Design of data driver (nrz, rz, mixing), output termination, T-coil and associated circuits for DAC.
5. Design Verification, improvements RFADC input driver (with DSA) in 7nm.
6. Designed very high bandwidth/gain-bandwidth and high linearity ADC input drivers and sample/hold circuits for RF-ADCs.

RF DACduty cycle correctorhigh resolution TDChigh speed comparatorAnalog Circuit DesignRF

Melexis

Lead Designer

Jul 2018 – Sep 2019 · 1 yr 2 mos · Bevaix, Canton of Neuchâtel, Switzerland

1. Lead designer of latest product line of Melexis position sensors: MLX90371.
2. Review design of all the analog blocks for the chip e.g. amplifiers, filters, oscillator, BGR, LDO, ADC, DAC and output driver and ensure design on time meeting all the specifications.
2. Ensuring circuit functionality especially under heavy (36dBm) DPI and power cut.
3. Documentation, drafting analog specifications, chip floor-planning, layout review.
4. Tracked design status and effort of the team including analog circuit designers and layout engineers and ensured tape out on time.
5. Involved in Boot-camp for chip testing.

position sensorsanalog blockschip floor-planningAnalog Circuit Design

Semtech

Senior RF Engineer

May 2017 – Jun 2018 · 1 yr 1 mo · St-Blaise, Canton of Neuchâtel, Switzerland

1. Design of analog feedback loop tuned phase shifters from 2.6GHz to 1.2GHz for IQ clock generations in PLL.
2. Design of 80dB SNDR 32MS/s Continous Time Delta Sigma ADC for signal BW upto 500kHz.
3. Design of analog base band for Rx. 3rd order tunable bandwidth Anti-Alias Filter with built in VGA and 9b 32MS/s Async SAR ADC (Signal BW from 3-12MHz).
4. Design of ultra low power (current consumption~150nA) band-gap reference.
5. Validation of POR and LDO.

phase shiftersContinous Time Delta Sigma ADCband-gap referenceAnalog Circuit DesignRF

Stmicroelectronics

6 roles

Member Of Technical Staff

Nov 2016 – Apr 2017 · 5 mos

Staff Engineer

Jan 2015 – Jan 2017 · 2 yrs

1. Member of Analog Design Expertise Group.
2. Design of Ultra low Power circuits for IoT and Wearables: sub 100nW BGR and XO in 40nm CMOS. Paper appeared in IEEE CICC 2017 held in Austin, Texas.
3. Assisted the design of instrumentation amplifiers, R2R and low-THD op-amps in BCD technologies.
3. Designed 1m-50mA >90% efficient@full load (CCM/DCM) voltage-mode buck converter in 28-FDSOI.
4. -93dBm Sensitivity BLE Receiver (Low IF) in 40nm CMOS. Top level specs for all receiver blocks, designer of RF front end and analog base-band (LNA, mixer, VGA, fiter). Assisted the design of 9b 24MSPS Async SAR.
5. 200mA Digital LDO with Analog-Assisted Dynamic Reference Correction: lead to US Patent and paper at IEEE MidWest Symposium on Circuits and Systems in Boston.

analog base bandlow power circuitsAnalog Circuit Design

Technical Leader

Jan 2014 – Jan 2015 · 1 yr

1. Design verification of analog base band (LPF+VGA+DC Comp. Loop) for 24GHz Transceiver for Back-Haul.
2. Designer of Space-Grade Radiation Hardened PLL- 200MHz-1200MHz output and 20MHz to 100MHz input with clock-tree insertion and low jitter.
3. Designer of ultra low power and low area 32KHz input PLL for audio codec. The PLL offers lowest jitter and lowest area reported till date. Paper presented at IEEE ESSCIRC (2016) held in Lausanne, Switzerland.

design verificationlow power PLLAnalog Circuit Design

Technical Leader

Jan 2013 – Jan 2014 · 1 yr

1. Designer of 5.28GHz LC VCO PLL, 2.64GHz/1.76GHz PLL for WiGiG BaseBand.
2. Designer of Wide Range Temperature Compensated 9GHz to 13GHz LC VCO (this is used inside a reference-less CDR targetted for SONET and other HS links). Frequency compensated to 1000ppm and temperature compensated to 500ppm

design verificationlow area PLLAnalog Circuit Design

Senior Analog Design Engineer

Promoted

Jan 2012 – Jan 2013 · 1 yr

1. Involved in design of PLL, FLL, oscillator (LC+ring+RC etc..), accurate charge pumps, loop filters, regulators, band-gap references, phase frequency detectors, frequency to voltage convertors, TDCs
2. Designer of ultra low power 32kHz PLL for Audio Codec. The design has state-of-art power-jitter FOM and has been presented at IEEE ESSCIRC (2014), held in Italy.
3. Co-Designer of 3GHz to 5GHz output and 10MHz to 50MHz input Fractional PLL in 28nm FDSOI

VCOPLLAnalog Circuit Design

Analog Design Engineer

Jan 2009 – Jan 2012 · 3 yrs

1. Main responsibility to design crystal oscillator and RC oscillators
2. Designed crystal oscillators (32kHz, 30MHz with Automatic Amplitude Control) in several technology nodes (65nm, 40nm, 32nm, 28nmm)
3. Invented state-of-art (2009) lowest power 32kHz XO
3. Designer of PVT compensated CMOS oscillators (30MHz with +/-1% accuracy)
4. Designed several voltage and current-reference circuits (band-gap), op-amps, high speed comparators and current DACs (low speed but highly accurate) for digital FLL

PLLFLLoscillatorAnalog Circuit Design