Hitesh Garg

CEO

Bengaluru, Karnataka, India29 yrs 2 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Analog-Mixed Signal product development.
  • Proven leadership in building high-performing AMS teams.
  • Extensive experience in semiconductor industry.
Stackforce AI infers this person is a Semiconductor Engineering Leader with expertise in Analog and Mixed Signal design.

Contact

LinkedIn

Skills

Core Skills

AnalogMixed Signal

Other Skills

ARMASICAnalog Circuit DesignAnalog IP DevelopmentAnalog IP Portfolio ManagementApplication-Specific Integrated Circuits (ASIC)Architecture DesignBusiness DevelopmentCDR PLL DesignCMOSCircuit DesignDebuggingDigital Signal ProcessorsEmbedded SoftwareHardware Architecture

About

Development of State of Art Analog-Mix Signal Products, Sub-Systems and IPs. Building highly Innovative/competent AMS teams.

Experience

Nxp semiconductors

2 roles

Vice President and India Country Manager

Promoted

Nov 2022 – Present · 3 yrs 4 mos

General Manager AMSIP and Site Head

Aug 2008 – Present · 17 yrs 7 mos

  • General Manager of AMSIP Organisation
  • Site Head of NXP Bangalore

Conexant systems

Engineering Manager, AMS

Mar 2006 – Aug 2008 · 2 yrs 5 mos · Bangalore

  • Complete PHY and Analog IP Development for multiple interface standards e.g. USB 2.0, Gigabit Ethernet, MoCA and for PON ICs. Differentiating AMSIP development for STB and Broadband access Business Units.
PHY DevelopmentAnalog IP DevelopmentInterface StandardsAnalogMixed Signal

Alliance semiconductor

Lead Engineer

Aug 2003 – Mar 2006 · 2 yrs 7 mos · Bangalore

  • TX and CDR PLL design for SGMII/Ethernet/HT bridge ICs.
TX DesignCDR PLL DesignAnalogMixed Signal

Microchip

Senior Engineer

Oct 2000 – Aug 2003 · 2 yrs 10 mos · Bangalore

  • Architecture and Design of PIC Microcontrollers. Ownership of Analog IP portfolio.
Architecture DesignAnalog IP Portfolio ManagementAnalogMixed Signal

Semiconductor complex limited

Member Design Development Team

Feb 1997 – Oct 2000 · 3 yrs 8 mos · Chandigarh

  • Design of Low Power ASICs for Hearing aid and Pacemaker applications
Low Power ASIC DesignAnalog

Education

Indian Institute of Management Bangalore

MBA — Management

Jan 2008 – Jan 2011

Grenoble Ecole de Management

MS — Management

Jan 2010 – Jan 2010

Guru Nanak Dev University

B.Tech — Electronics & Communication

Jan 1991 – Jan 1995

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