Abhishek Jain

CEO

Noida, Uttar Pradesh, India23 yrs 7 mos experience

Highly Stable

Key Highlights

Expert in EDA and Emulation technologies.
Led development of HDL Link co-simulation tool.
Extensive experience in customer support and training.

Stackforce AI infers this person is a specialist in EDA and Emulation technologies within the semiconductor industry.

Contact

Skills

Core Skills

EdaEmulationCo-simulation ToolFunctional Verification

Other Skills

APIsAdvance debug methodologyAlgorithmsCC++C/C++ClearCaseCo-ModelingCo-SimulationCoverage analysisCustomer EvaluationDFTData StructuresDebuggingDesign

About

Software Development Experience in the field of EDA especially Emulation ,co-modelling, DFT and Safety (Fault) technology. Working in the TBX technology of Veloce Emulator. Involved in the end-to-end design, development, verification and performance-optimization of Veloce tool for the Chip design industry. Also involved in multiple onsite tool evaluations and customer support. Skills: Algorithms, Data Structures, Object-Oriented Programming Software Languages: C, C++, Perl, Shell (Linux Platform) Hardware Languages: System Verilog and VHDL

Experience

Siemens eda (siemens digital industries software)

2 roles

Principal Architect

Promoted

Jan 2024 – Present · 2 yrs 2 mos

Architect

Jan 2022 – Feb 2024 · 2 yrs 1 mo

Design | Development | Verification | Optimization | Customer Evaluation/Support
EDA | Emulation | Safety (Fault) | DFT | Co-Modeling/Co-Simulation | Advance debug methodology
C/C++ | System-Verilog/VHDL | Perl/Shell

DesignDevelopmentVerificationOptimizationCustomer EvaluationSupport+12

Mentor graphics

5 roles

Principal Engineer

Promoted

Aug 2014 – Dec 2021 · 7 yrs 4 mos

Lead Member Consulting Staff

Aug 2010 – Jul 2014 · 3 yrs 11 mos

Member Consulting staff

Jan 2008 – Jul 2010 · 2 yrs 6 mos

Worked as a senior member and then lead in the co-simulation tool :HDL Link.
Involved in the support of different language constructs in system Verilog, Integration of tool with Hardware platform (Veloce), Development of low level APIs for communicating between hardware and software, Runtime performance optimization during emulation , Support for UVM/OVM and transaction recording for replay .
Performed onsite evaluation of tool at Intel, Mitsubishi and ST. Supported customers like Lucent, Fujitsu, Microsoft, Intel , Xerox, HiSilicon, General Dynamics, Nokia-Siemens.
Provided onsite training to customers and Application Engineers.

Co-simulation toolSystem VerilogIntegrationAPIsRuntime performance optimizationUVM/OVM+1

Lead Member Technical Staff

Promoted

Jan 2006 – Dec 2007 · 1 yr 11 mos

Senior Member Technical Staff

Dec 2003 – Dec 2005 · 2 yrs

Texas instruments

Design Engineer

Feb 2002 – Nov 2003 · 1 yr 9 mos · Greater Bengaluru Area

Worked as front end designer in wireless division. Involved in design, development (VHDL-Questa) , functional+design documentation, synthesis (DC), Linting (LEDA), Performance optimization(Power/Area), Formal verification (Formality), Coverage analysis (Line,toggle,branch) and functional testing (Local test bench based) of GDMA module in UMA/OMAP chip.
Latter on worked on Full chip integration of UMA and Gate level simulation.

VHDLFunctional verificationDesign documentationSynthesisLintingPerformance optimization+3