Sunil Bansal — Software Engineer
As an Emulation and Hardware-Assisted Verification Specialist, I bring over 13 years of experience in SoC design verification, and RTL and Gate-Level Emulation. My focus is on Pre-Silicon Verification on Emulators, i.e., Hardware-Assisted Verification, and Shift-Left Validation and Software Development, ensuring the highest standards of design accuracy and reliability. My expertise includes working with Emulation platforms such as ZeBu, Veloce, and Palladium, as well as advanced verification methodologies like UVM (Universal Verification Methodology) and UPF (Unified Power Format). I specialize in RTL and Gate-Level Emulation, which allows for efficient validation of complex designs and early detection of potential issues. I am also responsible for developing Emulation models to accelerate DFT (Design for Test) simulations and tester pattern development in Pre-Silicon stages, further optimizing verification workflows and enhancing overall design quality. I am committed to continuous learning and innovation, always seeking to stay ahead of industry trends and advancements. My strong problem-solving skills, coupled with my ability to collaborate effectively with cross-functional teams, have been key to my success in delivering high-quality results. Let's connect and explore how we can drive innovation and excellence in Emulation domain and Hardware-Assisted Verification together.
Stackforce AI infers this person is a Semiconductor Verification Specialist with expertise in Emulation and Hardware-Assisted Verification.
Location: Assandh, Haryana, India
Experience: 14 yrs
Skills
- Emulation
- Verification
Career Highlights
- Over 13 years of experience in SoC design verification.
- Expertise in Hardware-Assisted Verification and Emulation.
- Strong problem-solving and collaboration skills.
Work Experience
NXP Semiconductors
Sr. Principal Engineer, Emulation and Hardware Assisted Verification (11 mos)
Principal Design Verification and Emulation Engineer (2 yrs 11 mos)
Staff Design Verification and Emulation Engineer (1 yr 8 mos)
Lead Design Verification and Emulation Engineer (2 yrs 11 mos)
Mentor Graphics
Emulation Speciaist (1 yr 11 mos)
Senior Member Technical Staff (1 yr 11 mos)
Member Technical Staff (11 mos)
Higher Education Program Trainee (1 mo)
DCRUST
Training and Placement Coordinator (10 mos)
Education
Bachelor of Technology (B.Tech.) at D.C.R.U.S.T.
Senior School at Cambridge Public School, Assandh
Secondary School at Cambridge Public School, Assandh