Mar 2021 – Sep 2023 · 2 yrs 6 mos

• Lead the design and development of various ISG Broadband(PPPoE) Features on ASR1k and ISR4K Series Routing Platforms
• Extreme Customer Focus and have provided timely solutions to some of the most complex issues faced in Broadband, Etherchannel & Cisco TrustSec features in Customer Networks of Google, Microsoft, Deutsche Bank, SWISSCOM, PALTEL, Vodafone, NTT, etc
• Cross functional discussions with Product Marketing, Account and Sales team to decide Dynamic Link Exchange Protocol(DLEP) feature prioritization
• Developed Dynamic Link Exchange Protocol(DLEP) Feature in Radio Aware Routing(RAR) & added IPv6, QoS Feature Support for C8Kv IOSXE Router to be used by US Military, a project worth of 30Mn$
• Developed Complete Automation Testsuite for DLEP Feature in Python on Cisco's Pyats Framework on VSCode IDE. Major automated routing features for DLEP includes OSPF, EIGRP, QoS, IPv4 Dual Stack, IPv6 Dual Stack, Multicast, etc
• Lead the design & development of Complete Multicast Feature for DLEP Protocol on ASR1k Series & Embedded Services(ESR) Routing Platforms for Radio Aware Routing
• Major Contribution to development of 64BIT Datapath Feature for ASR1k Series Routing Platforms
• Part of SDWAN Service Chaining Feature for ASR1k Series Routing Platform
• Brought 70+ defects to closures. And fixed most of the day one behaviour issue.

Aug 2018 – Feb 2021 · 2 yrs 6 mos

• Lead the Design & Development of Flow based & vlan Manual based Load Balancing Algorithm for Etherchannel Feature on ASR1k Router
• Designed & developed Deep Packet Inspection Hash Algorithm Feature for loadbalancing PPPoE traffic on Etherchannel member links
• Contributed to Ultima Thule Project which involved complex task of unifying autonomous & controller mode in single image for SDWAN Supported Routing devices
• Involved in Design & Development of NETCONF, ConfD & Yang-Data Modelling features for configuring Network Devices via vManage for Catalyst Edge Platforms
• Lead the development of Cisco Trustsec Feature(CTS) on ASR1k Routing Platforms which uses software-defined segmentation to simplify the provisioning of network access, accelerate security operations, & consistently enforce policy anywhere in the network
• Contributed to SDA-ACI Dataplane integration UIT Plan
• Developed Automated TestSuite for Cisco Trustsec feature with ML based VSCode IDE & vtest AUT UI Tool
• Provided innovative solutions to Customers Complex issues related to Etherchannel, Cisco TrustSec datapath & MPLS TE-FRR features
• Brought 80+ defects to closures. And fixed most of the day one behaviour issue.

Jan 2018 – Jun 2018 · 5 mos · bangalore

• Successfully completed two projects under Six months of internship, which included;
• Performance improvement of PPPoE Client Emulation on ASR1k Series Aggregation router: Fine-tuned the PPPoE emulation module, which helps in generating PPPoE control packets at the much faster rate that eventually improves the Calls per second(CPS) at higher number of sessions. Made use of Image Profiling Tool called Flamegraph to identify the execution times of datapath functions
• Hosting TRex application as a container on ISR4k router for sending PPPoE encapsulated packets: Hosted a realistic Traffic Generator (TRex) inside a container over ISR4k router, which can be used to send the PPPoE sessions traffic through TRex inside the container on ISR4k router, thus acting as a virtual Traffic Generator, instead of relying on third party expensive traffic generators like Spirent & Ixia, as being used by Cisco for generating traffic over router
• TRex On UCS Box: Incorporated & successfully tested the role of virtual realistic Traffic Generator App (TRex) on the Cisco’s Unified Computing System (UCS) & monitored the link speed through GUI App of TRex on UCS as Client & ASR1k as Server

Aug 2016 – Dec 2017 · 1 yr 4 mos · Rajasthan, India · On-site

• Teaching Assistant for some of the courses in Advanced Digital Communication & Signal Processing
• Responsible for creating assignment, Lab exams, conducting recitation sessions based on MATLAB in Advanced Digital Signal Processing & end Semester Project Evaluation based on MATLAB

Jun 2014 – Apr 2015 · 10 mos · Mumbai, Maharashtra, India · On-site

• Design & Developed a cost effective technique for Bulk testing of embedded circuit boards using FPGA, for which a Hardware board based on Numato FPGA board was designed & programmed using Verilog codes in FPGA for testing of the prototype board

Nov 2013 – Dec 2013 · 1 mo · Mumbai Area, India

• Learnt embedded c, Arduino programming, AVR programming, sensor interfacing.

Nov 2013 – Dec 2013 · 1 mo · Mumbai Area, India

• In this project, we designed a bot whose motion was controlled through a wireless distance communication in which we used the ATMEL microcontroller as a main controller along with transmitter and receiver module based on ASK modulation Principle.