Naren Vallepalli

CEO

Bengaluru, Karnataka, India31 yrs 5 mos experience

Highly Stable

Key Highlights

Led a team of 500 in chip innovation.
30 years of experience in semiconductor industry.
Expert in AI and cloud infrastructure development.

Stackforce AI infers this person is a leader in semiconductor design and engineering for AI and cloud infrastructure.

Contact

Skills

Core Skills

Server SocsProduct DevelopmentMobile Chipset DesignPower ManagementServer Soc DesignTechnical LeadershipProcessor DevelopmentProcess TechnologyMixed Signal Design

Other Skills

ASICAnalog & Mixed Signal IPsApplication-Specific Integrated Circuits (ASIC)CMOSCapacitive sensingClient SOCsCustom server processorDebuggingEDAEdge ServerEmbedded SystemsEngineering ManagementExecution strategyFPGAFunctional Verification

About

I lead the Google Cloud’s Chip Innovation Infrastructure (CI2) team in India, driving the development of custom, workload-optimized chips—including TPUs and Axion CPUs—that are foundational to Google’s AI and Cloud infrastructure. My work is about designing the future, one transistor at a time. With 30 years in the semiconductor industry, I have amassed a deep, diversified track record across Mobile, IoT, Server, and PMIC chip architectures. I am passionate about moving beyond traditional silos to create an integrated engineering culture where hardware and software teams co-design solutions from the ground up. This approach accelerates innovation and ensures our silicon delivers maximum business impact. My leadership centers on scaling high-performance global teams—I have built and led groups of up to 500 people across the U.S. and India. I thrive on cultivating an environment defined by high ethical standards, open communication, and the energy required to tackle the world's most complex challenges in artificial intelligence and cloud computing.

Experience

Google

Site Lead, Google Cloud's Chip Innovation Infrastructure (CI2)

Nov 2022 – Present · 3 yrs 4 mos · Bengaluru, Karnataka, India

Intel corporation

3 roles

Vice President Of Engineering

Promoted

Sep 2016 – Nov 2022 · 6 yrs 2 mos · Bengaluru, Karnataka, India

Edge Server: Leading the pathfinding and technical readiness effort for the custom server processor for deployment at the Edge.
Client SOCs: Leadership role in designing and productizing SOCs for the multi-billion-dollar Desktop and Essential market segments on the cutting-edge process technology nodes.
Analog & Power Products: Delivered best-in-class and highly integrated PMICs with the best BOM area and aggressive form factor designs for Intel’s low-power client segment. In addition, this team continues to deliver differentiated analog and mixed-signal IPs in advanced Intel and external technology nodes.
Organization: Focuses on Innovation charter and on nurturing talent, increasing diversity, and building a strong technical leadership pipeline to address needs in the Server & Client markets.

Edge ServerCustom server processorClient SOCsPMICsAnalog & Mixed Signal IPsServer SOCs+1

Director of Engineering

Promoted

Jul 2006 – Apr 2013 · 6 yrs 9 mos

Server SOCs for Data Center Segments: Leadership role in designing and productizing Server SOCs for datacenter market segment on the cutting-edge process technology nodes. Core member of the execution leadership team – driving pathfinding, technical readiness, execution strategy, efficiency initiatives, risk mitigation processes, post-silicon preparedness and execution. Successfully designed three server chips and productized two server chips.

Server SOCsTechnical readinessExecution strategyServer SOC DesignTechnical Leadership

Engineering Manager

May 1996 – Jul 2006 · 10 yrs 2 mos

Product Development: Member of many client and server processor development teams primarily focusing on IO design, Clocking, SRAM memories and Low Power Analog Circuits.
Process Technology: Delivered lead test vehicles to accelerate technology and design IP learning towards certification.

Product DevelopmentIO designLow Power Analog CircuitsProcessor DevelopmentProcess Technology

Qualcomm

Director of Engineering

Apr 2013 – Sep 2016 · 3 yrs 5 mos · Bengaluru, Karnataka, India

Mobile Chipset/Platform Architecture: Led platform architecture for mobile devices (phone, tablets, IOT, wearables, and media set-top boxes) for the mid and value tier market segments. The team conducted exhaustive technical analysis needed to optimize the target platform for the overall unit cost, chipset partitioning, PCB Area, eBOM, PDN, Signal Integrity, Power delivery and interface performance requirements.
PMIC Systems & Integration: Led the team to define, specify, configure, integrate and deliver PMICs that meet the chipsets and customer’s needs. The power management functions include Input power management, power conditioning, regulation & distribution, clocks, lighting, haptics and control.

Mobile Chipset ArchitectureTechnical analysisPMIC Systems & IntegrationMobile Chipset DesignPower Management