Animesh Kishore

CTO

Bengaluru, Karnataka, India15 yrs 6 mos experience

Most Likely To SwitchAI ML Practitioner

Key Highlights

Expert in AI/ML accelerator driver development.
Proven track record in display technology for automotive.
Extensive experience with high-performance networking solutions.

Stackforce AI infers this person is a highly skilled Embedded Systems and Display Technology expert with a focus on AI/ML and networking.

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Skills

Core Skills

Ai/mlEmbedded SystemsNetworkingDisplay Technology

Other Skills

AI/ML accelerator driversAI/ML solutionsAlgorithmsApplication-Specific Integrated Circuits (ASIC)AutomotiveCC++Computer ArchitectureDRMData StructuresDebuggingDisplayPortDrmEmbeddedEmbedded C

About

- Worked on INTEL Habana Gaudi AI/ML accelerator. SoCs from SAMSUNG Exynos, QUALCOMM Snapdragon and NVIDIA Tegra. - Linux kernel and QNX, device driver development and commercialization for mobile and automotive. - AI/ML accelerator linux kernel/userspace drivers. - Display drivers, network and graphics architecture. - IB verbs Infiniband RoCEv2 and rdma-core. - Display pixel pipeline. V4L2, DRM, Fbdev on linux. WFD on QNX. - Display interface protocols. HDMI, MIPI DSI, eDP and DisplayPort. - Panel bring-up on Android and QNX. Feel free to contact me at animesh.kishore@gmail.com

Experience

Samsung r&d institute india - bangalore

2 roles

Associate Technical Director

Promoted

Jun 2023 – Present · 2 yrs 9 mos · Bangalore, India

AI/ML solutions, Exynos mobile & automotive

AI/ML solutionsExynos mobileautomotiveAI/MLEmbedded Systems

Senior Staff Engineer

Oct 2019 – Feb 2021 · 1 yr 4 mos · Bangalore, India

Leading Automotive Display and Graphics team
Working on QNX RTOS and Linux, Exynos Automotive SoC.
Authored triple buffered display pipeline. Reduces frame update latency leading to higher refresh rate.
Implemented linux type workqueues and deferred work framework for QNX.
Architected graphics buffer sharing across OSs through hypervisor.
Architected arbiter for GPU sharing across OSs through hypervisor.
Authored end-to-end(i.e. connector to window manager) display pipeline hotplug framework for QNX OpenWF.
Working on VESA Display Port MST for QNX.
Implemented VESA Display Port link training.
Bring-up for DSI2HDMI bridges for QNX, Linux and Android.
Commercialized display pipeline drivers for Samsung automotive customers.

QNX RTOSLinuxExynos Automotive SoCtriple buffered display pipelinegraphics buffer sharingVESA Display Port+2

Intel corporation

Embedded AI/ML Expert

Feb 2021 – Jun 2023 · 2 yrs 4 mos · Bangalore, India

Leading AI/ML accelerator drivers team
Working on heterogeneous Gaudi compute cores for data center, scaled using Infiniband RDMA(RoCEv2).
Wrote netdev linux driver for scale out management.
Authored IB verbs kernel and userspace(rdma-core) driver for scale up/out.
Working on upstreaming accelerator drivers.
Worked on data center network topology. L2 routing for scale up. L3 routing for scale out with multi-level switches.
Congestion control for optimum throughput.
Network packet encapsulation, VXLAN and NVGRE.
Implemented MPI collective communication operations.
Added on device MMU support for accessing fragmented host memory.
NIC compression for reducing network bandwidth.
Implemented HPC rendezvous operations.

AI/ML accelerator driversInfiniband RDMAnetdev linux driverdata center network topologycongestion controlnetwork packet encapsulation+5

Qualcomm

Senior Lead, Display Drivers

Dec 2016 – Oct 2019 · 2 yrs 10 mos · Hyderabad, India

Display pixel pipeline:
Alpha compositing.
Color space conversion and gamma correction.
Secure display pipeline for UI, video and camera.
Buffer synchronization fences. Staged android sync and mainline dma-buf fence drivers.
V4l2 mem2mem framework for memory writeback rotator.
2D Scalar.
Command and video mode operation.
Tear check for smart panel with internal frame buffer.
Timing engine for video mode panel.
Frame buffer state management and optimization.
Variable and adaptive refresh rate for power optimization.
Clock, memory bandwidth and regulator optimization.
Prefetch, programmable prefetch and amortized prefetch.
Pixel format, interleaved/pseudo-planar/planar, RGB/YUV, linear/tiled/block, compressed.
Extensively worked on commercialization issues with Qualcomm customers.
Architected post kernel boot, dynamically loadable display driver modules. Encompasses flicker free bootloader logo handoff to kernel.

display pixel pipelinealpha compositingcolor space conversionsecure display pipelinebuffer synchronization fencesDisplay Technology+1

Nvidia

Linux Display Drivers Lead

Sep 2010 – Dec 2016 · 6 yrs 3 mos · Hyderabad, India

HDMI:
Authored HDMI v2.0 kernel driver from scratch. Comprises of all essentials of v1.4b as well.
The driver is in production and compliance certified by HDMI LLC.
Wrote parser for EDID CEA extension block.
DisplayPort:
Authored DP v1.2 kernel driver from scratch.
The driver is in production and compliance certified by VESA.
Authored AUX channel driver for native and i2c transactions.
Added support for DP v1.3 YCbCr420 and BT2020.
Wrote parser for EDID base block and DPCD.
MIPI DSI:
Authored MIPI DSI kernel driver from scratch. Driver in production.
Worked on 15 panel bring-ups with vendors like Novatek, JDI, AUO, BOE, LG, Panasonic, Sharp, Toshiba, ZTE and Samsung.
Major composited architecture on Nvidia Tegra SoC:
1) Hotplug State Machine:
Manages debounce, spurious hpd events from monitor, EDID/ELD read failures, monitor capabilities update, notifications to userspace and other kernel drivers, suspend/wake display subsystem when monitor unplugged/plugged and flicker free display transition from bootloader to kernel.
On Tegra, integrated to HDMI and DisplayPort drivers. Though core logic is portable to any external display protocol and SoC.
For platform agnostic core logic, checkout my GitHub repository https://github.com/ankishore/hotplug-state-machine.
2) DisplayPort Link Training:
Manages all states of full and fast link training. Design takes care of all intricacies of clock recovery, channel equalization and bit-rate/lane reduction with supported levels and combinations of voltage swing, pre-emphasis and post-cursor2.
Core logic is portable to any HW architecture.
For platform agnostic core logic, checkout my GitHub repository https://github.com/ankishore/DisplayPort-link-training
3) Aggressive power saving for DSI panels with internal frame buffer:
▸ Helps power down display subsystem when user application is not actively refreshing.
▸ Coupled with DVFS it achieves system wide power saving specially during OS idle.