Prateek Omer

Software Engineer

Bengaluru, Karnataka, India10 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Pioneered AI/ML efforts for productivity improvements
Achieved 5%+ power improvements YOY
Awarded CDNLive-2025 Pest paper award

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in GPU architecture and power optimization.

Contact

Skills

Core Skills

Power OptimizationPhysical DesignRtl-gds ImplementationPpa OptimizationPhysical SynthesisFormal VerificationDft

Other Skills

Engineering LeadershipAI/MLPower EstimationPower AnalysisRTL-GDSPPATclDigital DesignsSynthesisSTAECOPerlPrimetimeSynopsys PrimetimeTcl-Tk

About

Experienced front-end implementation Engineer with enthusiasm to learn and focuses on delivering high performance designs and automating work to make life easy. Apart from Job I have also worked on some technologies like Machine learning/Embedded systems/Android development etc. and I am open to learn new upcoming technologies.

Experience

10 yrs 11 mos

Total Experience

5 yrs 5 mos

Average Tenure

7 yrs 3 mos

Current Experience

Google

2 roles

Senior Silicon Engineer

Promoted

Nov 2024 – Present · 1 yr 6 mos · Bangalore · On-site

Methodology & PPA lead
Driving physical design methodology for GPU blocks like, Floorplan guidance, CTS methodology, STA correlation
Driving methodology for 5% YOY power improvements and achieving the same from last 2 generations
Pioneering AI/ML efforts to increase every day productivity for the team, Also, engaging with CAD to increase AI penetration in the teams
Work with cross-domain to better design DFT methodology, Memory integration, STA closure, help improve synergies between teams to improve overall PPA
Strategic Vendor Engagement : Engaging with Cadence and Synopsys for convergence and PPA efforts
Achievement: CDNLive-2025 Pest paper award
5%+ Power improvements YOY using implementation methodology updates
10% performance push while trying to minimize the area/leakage impact

Engineering LeadershipPower OptimizationPhysical Design

Silicon Engineer

Feb 2019 – Dec 2024 · 5 yrs 10 mos · Bangalore · On-site

Current Role & Responsibilities
=> Leading a team for RTL-GDS implementation of high performance compute IPs while, Managing all PPA activities on GPU subsystem
=> Providing RTL feedbacks for timing/power improvements through in depth synth/PD NL analysis
=> Expertise in Gate-Level Power optimization flows, UPF and CLP feedbacks
=> Working with the Design team and looking for Power improvement opportunities in RTL, Synth & PNR stages
=> Driving Power optimization across different IPs
=> Driving Internal TechForum for BLR-PD team
=> Look for opportunities to improve PPA through DFT-Arch improvements
=> Lead LEC efforts on all GPU-IPs
=> Look at VCLP clean for Complex Power-Domain designs.
=> Engagement EDA vendors for PPA push through tool improvements and new feature updates
Domain Expertise:
=> Expertise on RTL-GDS implementation of high performance compute IPs(primarily GPU)
=> Expertise in creating solutions for feedbacks from all signoff domains and taking to all signoff closure
=> Expertise in PPA optimization at synth and PNR implementation
=> Good understanding of RTL-Design and MBIST/DFT
=> Expertise in power Analysis on primePower
=> Expertise in Conformal LEC verification and Functional ECOs
=> Expertise in LP verification
=> Love to code and have expertise on perl/tcl
=> Currently collaborating with cross functional teams to improve power and performance

Power EstimationPower AnalysisRTL-GDS ImplementationPPA Optimization

Qualcomm

2 roles

Engineer

Promoted

Jun 2017 – Feb 2019 · 1 yr 8 mos

Currently coordinating synthesis team for delivering high performance GPUs.
Responsible for constraint generation for Synthesis and STA for GPUs.
Responsible for ECO implementation and their FV clousre.
Responsible for timing and wire congestion closure in physical-synthesis.
Expertise in Physical-Aware-synthesis and Formal verification closure.
Also worked on improving QOR by updating DFT flow and making it Physical-Aware.
Have worked on different technolgy nodes and owned front-end implementation for GPUs.
Worked on flow automation to improve QOR and reduce turn around time.
Also worked on updating Floorplans for physical aware synthesis.

TclDigital DesignsPhysical SynthesisFormal Verification

Associate Engineer

Jun 2015 – Feb 2019 · 3 yrs 8 mos

Joined as part of Graphics Hardware Implmentation Team that delivers Adreno GPUs as part of snapdragon MSMs.
Ramped up in synthesis/STA/FV for Graphics cores.
Also worked on basics of other flows like MBIST insertion/DFT insertion/PTPX/ECO flows.
Responsible for physical-synthesis/STA/FV closure of Graphic cores.
Contributed in developing automated work flows in Perl/TCL.

TclPerlPhysical SynthesisDFT