Sep 2022 – Sep 2023 · 1 yr · Remote

• Lead for NVM R&D; managed a geographically diverse team of process, device, and test engineers
• Company POC to a 300 mm research facility; defined process lot splits and electrical test requirements; conducted program reviews
• Coordinated Silicon mask design and taped out two research prototypes
• Demonstrated harsh environment applications previously thought unachievable for a memory technology
• Demonstrated operational device across spin-ON, PVD, and ALD processes in three distinct 4-inch fabs
• Principal Investigator for >$2.2M USG grants
• Technology and strategy roadmap; technical sales and marketing ; negotiated vendor budget and contracts

Oct 2020 – Feb 2023 · 2 yrs 4 mos · Remote

• Responsible for device physics, modeling, and design of two memory technologies (CeRAM and FeFET)
• Technology landscape analysis of Cerfe Labs' technology vs competition
• Contributed 10+ patents; assisted in IP strategy
• Established and streamlined the data pipeline in python
• Led customer discovery to validate the critical need for cryogenic memory in quantum hardware, thereby identifying a new market
• Co-ordinated team, conceptualized, wrote, and won highly competitive SBIR research grants (~ $1.4M)

Apr 2022 – Oct 2023 · 1 yr 6 mos · Dallas, Texas, United States · Hybrid

Oct 2018 – Oct 2020 · 2 yrs · San Jose, California · Hybrid

• Competitive analysis of NVM for embedded and non-embedded applications. The memory technologies analyzed included various flavors of ReRAM, CBRAM, Flash, PCM, FRAM, and FeFET.
• Assisted development of Arm's internal memory technology, which was later spun-off as Cerfe Labs. Developed models and help communicate the technology between process, device, architecture, and application groups. Interfaced with external industry and academic partners to co-develop the technology.
• Developed materials, process, device, and circuits IP
• Memory workload analysis for novel applications including AR, AI, etc.
• Resident Arm RSH expert for semiconductor physics and process technology. Assisted RSH teams with analyzing novel technology such as cryogenic computing, eDRAM, quantum computing, 3D monolithic integration, etc.
• Arm university representative to the SRC JUMP program. Organized student visit to Arm campus. Judged university research proposals.

Jun 2017 – Sep 2017 · 3 mos · Grenoble, France · On-site

• Spent summer in Grenoble (France) researching contact resistance between 2D materials and metals for application in logic and memory
• Performed first principle simulations using VASP toolkit to develop doping technique for optimizing the contact resistance

Jul 2015 – Sep 2015 · 2 mos · Milpitas,California

• Assisted in technology development for BiCS (3D NAND)
• Performed retention studies and correlated the results to process splits
• Developed programming modes for accessing random bits for retention study
• Use python to process and analyze the data

Jan 2014 – Sep 2018 · 4 yrs 8 mos · United States · On-site

• PhD thesis at intersection of material science, semiconductor, and condensed matter with focus on novel semiconductor materials such as MoS2. Thesis - "Two-dimensional devices and interfaces: From fundamentals to system models"
• Conducted high throughput parallel simulations studies based on TCAD, Molecular Dynamics, DFT, and NEGF.
• Performed electrical characterization and developed compact models. My compact models have be downloaded by >10,000 times on nanohub.org
• Developed a materials to system (M2S) level understanding of new technology by using the models to analyze process corners and system level performance
• I demonstrated fundamental limits of electrical contact resistance, thermal interface resistance, and electrostatic control in transistors

Jul 2011 – Jun 2013 · 1 yr 11 mos · Mumbai, India

• Teaching Assistant (TA) : The responsibility of TA included tutoring, evaluation of students, conducting and assessing exams, developing course material.
• Courses: CH 103 Introduction to Chemistry, EE 590 Foundation of Project, EE 672: Microelectronics Simulation Lab

May 2011 – Jul 2011 · 2 mos · Pittsburgh, PA, USA

• Developed non-destructive strategies to detect malicious circuits in FPGAs
• Design Trojans as small as ~10 transistor and demonstrated the that the change in path delay can be detected
• Developed a fingerprint of FPGA based on the path delays and used that to detect Trojan circuits