Sep 2019 – Dec 2023 · 4 yrs 3 mos · Mountain View, CA

• Architect and Design Image and Video Processing Modules
• Organizational impact with the Image Processing IPs shipped in Phones since Pixel6
• Lead/Initiate collaboration among algorithm, architecture, camera software, integration, and verification
• Plan and manage project priorities under tight resources and schedule working in a
• multi-functional, multi-geography context
• Direct and guide team members in consciously delivering HLS/RTL designs in an
• extremely tight schedule in the context of consumer electronics
• Collaborate with the Algorithm Team for Hardware Friendly Algorithms; Analyze and Optimize Algorithms and Architectures; Design IPs leveraging the efficiency High-Level Synthesis C; Perform Various Implementation and Verification Tasks; Create and Maintain Design/Verification Automation Tools

Jul 2019 – Sep 2019 · 2 mos · San Jose, CA

• Acquisition of NGCodec

Jul 2018 – Sep 2019 · 1 yr 2 mos · Sunnyvale, CA

• Working on the world's best video encoders with ultra-low latency and ultra-high compression efficiency and more: value-added advanced AI and deep learning processing!
• Architect and Design Hardware Modules inside Modern Video Encoders (AVC/HEVC/VP9/AV1)
• Design is done in HLS C/C++ using Vivado HLS targetting Xilinx FPGAs
• Develop Verification Environment in C++ and Verify with Raw Video Streams
• Develop and Maintain Regression Frameworks and Tools

Jan 2017 – Present · 9 yrs 2 mos · San Francisco Bay Area

• Angel investor focusing on early-stage ventures, especially enterprise-oriented startups with a B2B2C business model.

Oct 2015 – Jul 2018 · 2 yrs 9 mos · Cupertino

• Functional Verification of Core Graphics Components
• Unit Verification Lead - Lead a Team of 3 Collaborating on Various Verification Tasks
• Devise Verification Strategies and Manage Project Schedule for Timely RTL Delivery
• Participate in Architecting and Designing of Core Graphics Blocks in GPUs
• Architect and Code Constrained Random Stimulus Stack in C++
• Develop Scalable and Adaptable Verification Framework in UVM
• Drive Functional and Code Coverage Closure for High-Quality RTL Delivery
• Perform Performance and Power Verification in Unit

Aug 2013 – Oct 2015 · 2 yrs 2 mos · Santa Clara

• Unit Verification Engineer/Lead in Graphics Pipeline
• Devise Verification Strategies and Plan
• Architect and Code Constrained Random Stimulus Stack in C++ for Test Case Generation and Coverage Closure
• Formal Verification Techniques: C-to-RTL and Clock-Gating Verification
• Clock Domain Crossing Validation, Netlist Auditing, Power and Timing Closure
• Side Project: Refactor 5K Lines of Code with a New Set of APIs for Easier Test Writing

Jul 2011 – Aug 2013 · 2 yrs 1 mo · UC Berkeley

• Open Source FPGA Design for Custom Application Acceleration
• Developed the Specification and Designed an Open Source FPGA Generator in Chisel (a Berkeley Developed Hardware Description Language)
• Developed the Tool Flow for the Open Source FPGA
• White Paper: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-43.html
• Source Code Repo: https://github.com/haojunliu/OpenFPGA
• Multi-Cache on FPGA for Application Acceleration
• Designed an FPGA Based, Multi-Cache System with Cache Coherence Network for Transparent Application Acceleration
• Perform Profiling Against Traces and Generate Accelerators in Verilog
• Conference Paper: http://ieeexplore.ieee.org/document/6239808/

Sep 2009 – Jun 2011 · 1 yr 9 mos

• FPGA Video Processing Framework in Hardware Based MPI Protocol
• FPGA Partial Reconfiguration in a Message Passing Environment
• Conference Paper: http://ieeexplore.ieee.org/document/5695342
• Particle Simulation Acceleration Using High-Level Synthesis with Impulse C
• Project Report: http://individual.utoronto.ca/haojunliu/courses/ECE532_Report.pdf

Sep 2007 – Apr 2010 · 2 yrs 7 mos

• Lab Supervisor

May 2009 – Apr 2010 · 11 mos · Markham, Canada

• Software Engineer: Compiler Build and Test

Apr 2007 – Aug 2007 · 4 mos

• Math, Physics and Chemistry Teacher