Salahuddin .

Software Engineer

Bengaluru, Karnataka, India9 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

9+ years of experience in physical design.
Expertise in multi-million gate implementation.
Proficient in various technology nodes from 2nm to 22nm.

Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in Physical Design and VLSI methodologies.

Contact

Skills

Core Skills

Physical DesignVlsi

Other Skills

ASICApplication-Specific Integrated Circuits (ASIC)CTSCadenceCadence EncounterCadence SpectreCadence VirtuosoClock Tree SynthesisDC compilerDigital ElectronicsECOEDAEldo SPICEElectronicsFloorplanning

About

9+ years of experience in physical design. There converge several block-level partitions in challenging project environments with technology nodes. (2/3/4/5/7/10/14/22nm). • Involved in complete Physical Design flow with the following core competencies:: Floorplanning, Synthesis, Place/CTS/Route, STA / Timing closure, ECO flows and convergence, Post Route flows, Signoffs, Physical Verification (DRC, LVS). • Have good work exposure in multi-million gate implementation. • Worked on the multi-clock domain, multiply instantiated blocks, hierarchical blocks, and rectilinear blocks. • Technology node Experience: 2nm, 3nm, 4nm, 5nm, 7nm, 10 nm, 14nm, 22nm • Tools: Synopsys (FC, ICC2, PT, Calibre, ICV). • Programming skills in python, TCL, and Shell scripting.

Experience

Qualcomm

3 roles

Staff Engineer

Promoted

Nov 2024 – Present · 1 yr 4 mos

Senior Lead Engineer

Nov 2021 – Nov 2024 · 3 yrs

PDCAD Methodology

Senior Engineer

Jun 2019 – Nov 2021 · 2 yrs 5 mos

Intel corporation

Graphics hardware engineer

Mar 2017 – May 2019 · 2 yrs 2 mos · Bengaluru Area, India

I have worked in Intel Technology India Pvt Ltd, Bangalore in VPG team as a Graphics Hardware Engineer as a Part of a Graphics Processor Design team (structural designer) for Intel’s next generation processors. I have hands on experience in place & route, CTS, post Route (PR), ECO, Timing Closure, Logic synthesis. I have worked as Partition Execution Owner (PEO) in converging partitions for timing and shorts. I analyzed timing at different corners and applied timing fixes using manual ECO techniques. Responsible for STA for different corners of functional blocks & minimizing the short count. Good knowledge of timing concepts, Basic CMOS circuit design, signal integrity (crosstalk, EM, IR) fundamentals.

Place & RouteCTSECOTiming ClosureLogic synthesisSTA+2

Stmicroelectronics

Intern

Jan 2016 – Jul 2016 · 6 mos · Noida Area, India

Worked with High Speed Link team as a Mixed signal design and Modeling engineer.
Modeled Noise in PHY using Supply Noise Sensitivity Matrix from SPICE.
Learnings: Eldo SPICE, Unix, MATLAB

Eldo SPICEUnixMATLAB