Janak Patel

Software Engineer

Milpitas, California, United States15 yrs 5 mos experience
Highly Stable

Key Highlights

  • Experienced in Functional Verification and SoC design.
  • Proficient in Verilog and SystemVerilog.
  • Strong background in VLSI and ASIC development.
Stackforce AI infers this person is a VLSI Design Verification Engineer with expertise in Functional Verification and SoC architecture.

Contact

LinkedIn

Skills

Core Skills

Functional VerificationSoc

Other Skills

Application-Specific Integrated Circuits (ASIC)CDebuggingFormal VerificationPerlPhysical DesignSemiconductorsSystemVerilogUVMVerilogVery-Large-Scale Integration (VLSI)

Experience

15 yrs 5 mos
Total Experience
11 yrs 9 mos
Average Tenure
3 yrs 10 mos
Current Experience

Amazon web services (aws)

Design Verification Engineer

Jul 2022 – Present · 3 yrs 10 mos · Cupertino, California, United States

VerilogSystemVerilogSoCFunctional VerificationUVMFormal Verification

Einfochips (an arrow company)

3 roles

Technical Lead (Design Verification)

Oct 2016 – Sep 2022 · 5 yrs 11 mos

Senior Design Verification Engineer

Jun 2011 – Oct 2016 · 5 yrs 4 mos

Trainee Physical Design Engineer

Dec 2010 – Jun 2011 · 6 mos

Education

U.V.Patel College of Engineering - India

Bachelor of Technology (B.Tech.) — Electronics & communication Engineering

Jan 2007 – Jan 2011

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