Anjul Patney

CEO

Seattle, Washington, United States18 yrs 3 mos experience
Most Likely To SwitchAI Enabled

Key Highlights

  • Led AI research for gaming advancements.
  • Co-developed multiple deep learning graphics technologies.
  • Expert in visual perception and image quality metrics.
Stackforce AI infers this person is a leader in AI-driven graphics technology for gaming.

Contact

anjul.patney@gmail.comLinkedIn

Skills

Core Skills

Deep LearningArtificial Intelligence (ai)

Other Skills

ASICAlgorithmsCC++CUDACompilersComputer ArchitectureComputer GraphicsComputer ScienceComputer VisionGPGPUGPUHigh Performance ComputingImage ProcessingImage Quality

About

I lead a product-oriented research team in the area of AI for gaming. Our research is centered around AI, computer graphics, and visual perception. My work has led to advances in deep-learning for real-time graphics (co-developed DLSS 4, Project G-Assist, RTX HDR, RTX Dynamic Vibrance, DLSS 1.0), perceptual metrics for image quality (FovVideoVDP), foveated rendering for VR, and VR redirected walking. I update my home page more frequently: https://anjulpatney.com

Experience

Nvidia

2 roles

Senior System Software Manager

Promoted

Aug 2023 – Present · 2 yrs 7 mos · Greater Seattle Area

Principal Research Scientist

Mar 2021 – Jul 2023 · 2 yrs 4 mos · Greater Seattle Area

Deep LearningImage QualityVisual PerceptionVision ScienceArtificial Intelligence (AI)

Facebook

Research Scientist

Jun 2019 – Mar 2021 · 1 yr 9 mos · Greater Seattle Area

Deep LearningImage QualityVisual PerceptionVision ScienceArtificial Intelligence (AI)

Nvidia

5 roles

Senior Research Scientist

Oct 2015 – May 2019 · 3 yrs 7 mos

Deep LearningVisual PerceptionArtificial Intelligence (AI)

Research Scientist

Jan 2014 – Oct 2015 · 1 yr 9 mos

Research Scientist

Jul 2013 – Jan 2014 · 6 mos

Research Intern

Jun 2010 – Sep 2010 · 3 mos

  • Designed algorithms and architectures for fast, efficient, and programmable triangle rasterization algorithms; authored two patent applications.

Research Intern

Jun 2009 – Sep 2009 · 3 mos

  • Designed a compiler method to avoid register bank conflicts in highly parallel compute devices

Intel

Graduate Technical Intern

Jun 2008 – Sep 2008 · 3 mos

  • Part of the Larrabee Architecture team in the Intel Visual Computing Group.

Uc davis

Ph.D. Candidate

Sep 2007 – Jun 2013 · 5 yrs 9 mos

Nvidia bangalore

Summer Intern

May 2006 – Jul 2006 · 2 mos

  • Developed tools for design automation of ASIC designs for NVIDIA MCPs

Education

University of California, Davis

PhD — Electrical & Computer Engineering

Jan 2007 – Jan 2013

Indian Institute of Technology, Delhi

B. Tech. — Electrical Engineering

Jan 2003 – Jan 2007

Apeejay Pitampura

Elementary — Middle and High School

Jan 1989 – Jan 2003

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