Dec 2019 – Jan 2023 · 3 yrs 1 mo

• Responsible for leading a small team involved in projecting and analyzing power for graphics IPs

Jun 2017 – Dec 2019 · 2 yrs 6 mos

• Responsible for leading a small team involved in projecting and analyzing power for graphics IPs

Jun 2009 – Jun 2017 · 8 yrs

• Responsible for hiring, bringing up and managing teams for each of the following activities from the scratch,
• o Perf modeling: Modeling portions of GPU to aid arch feature decisions in those modules.
• o Architecture Lab: Lab plays leadership role in the performance debug, calibration and correlation of performance and power projection models
• o Power modeling: A comprehensive methodology of power modeling was developed that is used in feature go-no go decisions at path finding stage and for tracking power during execution.
• o Competitive Analysis: A comprehensive comparison of the architecture was done in terms of performance, power and area and BW requirement with respect to competition. Further analysis were done to root cause to architectural deficiencies/advantages.
• o Workload characterization & high level Arch tools: The team developed methodology for graphics workload characterization using high level simulators. Trace based simulators drove several initial cluster level arch path finding studies.
• During a significant portion of this duration, responsibility included aligning various arch study tools spread across different Geos, understanding their flows and dependencies, solving bottlenecks and negotiating SLAs for those dependencies and escalating to the right level where required.

Aug 2007 – Mar 2008 · 7 mos · Bengaluru Area, India

• Responsible for the modeling, analysis and conducting performance studies for future multi-core a server microprocessor architecture.
• These C++ performance models are built using the concepts of ports and clock provided by a set of simulator building blocks.
• Towards the end of the project became the sole member of the Bangalore microprocessor architecture and planning group owning the on die interconnect module of this simulator and fixing the bugs across the modules.
• During this time several architectural studies were conducted for topology, bandwidth and latency analysis of the uncore interconnect architecture.

Mar 2008 – Jun 2009 · 1 yr 3 mos · Bengaluru Area, India

• Conducted early path finding studies for low power GPU architecture.
• Was part of the team responsible for performance modeling of the video motion estimation engine.
• Lead the development of a GPU uncore performance model in a record time and conducted weekly performance studies/presentation. The studies resulted in several changes for the project.
• Undertook a study on speeding up a system C based performance simulator by parallel execution on several cores – The work was later published in an international conference,

Sep 2006 – Jul 2007 · 10 mos · Bengaluru Area, India

• Responsible for the development of BIOS for Mobile platforms based on EFI Framework.

Jan 2005 – Aug 2006 · 1 yr 7 mos · Bengaluru Area, India

• As a senior component design engineer, my key roles were
• Interface to design team for solving and clarifying issues brought forward by firmware teams.
• Act as a single point contact of the design team for the other internal teams like tech marketing , CPU validation etc located at different parts of the world.
• Track and resolve global architectural issues after working with the design and architectural team.
• Filed 5 patents in the area of new feature definition for many core microprocessor that enables the simultaneous usage of these processors for many operating systems using hardware assisted techniques.

Oct 2001 – Jan 2005 · 3 yrs 3 mos · Santa Clara

• Development of System Abstraction Layer of the BIOS for the validation platforms of future Itanium series processors. The job involves the following:-
• Development and maintenance of IA-64 (Itanium ) assembly language code for system abstraction layer for validation platforms.
• Planning, enabling and debugging firmware, hardware and software bugs in platform and in firmware for upcoming processors.
• Platform debug using Logic Analyzers, oscilloscope and In Target probes (JTAG debugger) to help the CPU validation team in isolating the CPU bugs from platform issues.
• Participation in power on of various IA64 CPUs

Jan 2001 – Aug 2001 · 7 mos · Sunnyvale, CA

• Implemented the firmware for MPEG2 video transrating algorithm on a TMS320C6x DSP communicating to a host processor. Ported the multithreaded algorthm in C++ on windows platform to C and Assembly language program on DSP running DSPBIOS (A proprietary RTOS from Texas Instruments); Designed and implemented the driver modules and interfaces for RPC calls and bulk data transfer between the host processor and a DSP ; Developed DMA Engines which queues up internal and external DMA requests. Designed and implemented buffer management techniques for efficient use of internal memory. Optimized select portions of the code using assembly language and the algorithm suited for the specific DSP processor and board architecture. (Example:- Implementation of Variable Length Decoding ); Debugged the code using simulator and JTAG emulator..

Jun 2000 – Jan 2001 · 7 mos · San Jose, CA

• Involved in the MGX8260 media gateway project. Tested and debugged code for reducndancy and software upgrade/downgrade running on a VxWorks platform. Developed a tool for editing the configuration of the media gateway by altering the data base files in binary. Wrote an installation software using PERL.

Nov 1998 – May 2000 · 1 yr 6 mos · Eindhoven Area, Netherlands & Bengaluru India

• Involved in the development of a reusable TV software using an indigenous component based technology. Developed certain firmware modules of the infrastructure (in C and Assembly language of 8051 based TV processor) which acted like an operating system for TV. Infrastructure was built around a small multithreaded RTOS called CMX. A timer server module and a driver for teletext data decoding unit which uses odd parity, hamming8/4, and hamming24/18 decoding for teletext data were implemented.

Oct 1997 – Oct 1998 · 1 yr · Bengaluru Area, India

• Silicon Automation Systems (India) PVT LTD, Bangalore, India.
• Implementation of MPEG2 video for HDTV application using a Data Driven Media Processor (DDMP) from Sharp. Part of the team responsible for defining the fixed point instruction set for the new data driven media processor (DDMP from Sharp) for HDTV application. Conducted performance studies of various algorithms using MATLAB and C. Wrote C programs to simulate the newly designed instructions at the functional processor level. Programmed the data driven processor for the IDCT, Motion compensation and audio decoding. Performed functional validation and code review of the ASIC Parser, VLD and other supporting logic written in Verilog HDL.

Apr 1997 – Oct 1997 · 6 mos · Bengaluru Area, India

• Involved in the design and implementation of the firmware for a Security System based on Digital Video Telephony, using ADSP 2181 as the embedded DSP processor.Wrote and optimized code in assembly language for the various modules. Involved in the system controller and UI module state machine design and implementation. Designed and implemented a motion detection unit from the digital video. Involved in the integration of the H.261 compliant Video module, G.711 module and network modules. -Simulated and genarated test vectors for motion detection algorithm using MATLAB