Suvrat Tedia

Product Manager

San Jose, California, United States9 yrs 5 mos experience

Highly Stable

Key Highlights

Expert in VLSI and Embedded Systems development.
Proven track record in yield improvement and reliability engineering.
Strong background in FPGA development and performance measurement.

Stackforce AI infers this person is a VLSI and Embedded Systems expert with a focus on reliability and yield improvement.

Contact

Skills

Core Skills

VlsiData AnalysisReliability EngineeringStatistical AnalysisEmbedded SystemsFpga Development

Other Skills

Assembly LanguageCC++CAD ToolsCadence SpectreCadence VirtuosoComponent QualificationData StructuresDesign for ManufacturabilityDesign of ExperimentElectrical Failure AnalysisFPGAMatlabMicrosoft ExcelMicrosoft Office

Experience

Sandisk

Product Development Engineer

Feb 2025 – Present · 1 yr 1 mo · Milpitas, California, United States · On-site

Western digital

Staff Engineer - Product Engineering

Feb 2022 – Feb 2025 · 3 yrs · Milpitas, California, United States

Intel corporation

2 roles

3D NAND Product Development Engineer

Mar 2021 – Feb 2022 · 11 mos · Folsom, California, United States

Working with design teams in developing solutions for Design for Manufacturability including new test modes for effective screens and stresses development, simulations and validation of test modes and help debug design related issues.
Ensure product specifications are met working with design teams.
Responsible for developing Wafer Sort/Probe tests and Yield/Fab Yield improvement.
Responsible for Electrical Failure Analysis and development of new stresses and screens for DPM improvement and yield improvement on the new upcoming technologies and yield sustainability on mature products.
Work with several cross-functional teams for resolving product level issues.
Data Analysis and Parsing skills to analysis high volume data for Quality improvement and Yield improvement.

Design for ManufacturabilityElectrical Failure AnalysisData AnalysisYield ImprovementVLSI

3D NAND Product Quality,Reliability R&D Engineer

Dec 2017 – Feb 2021 · 3 yrs 2 mos · Folsom, California, United States

● Define component qualification flow/plan based on industry standard (JEDEC) and customer usage specifications and conditions
● Build product reliability acceleration models by fitting extracting parameters from designed process/experiment data.
● Proceed Design of Experiment (DOE) and electrical /physical failure analysis (EFA/PFA) for production risk assessment and provide corrective actions to product and manufacturing teams.
● Create bench test scripts to streamline the testing process in order to return faster results.
● Pull fabrication/probe/backend data for statistical analysis to achieve systematic yield improvement and overall DPM evaluation.

Component QualificationReliability Acceleration ModelsDesign of ExperimentStatistical AnalysisReliability Engineering

University of florida

Graduate Research Assistant - Center for High Performance Reconfigurable Computing (CHREC)

Mar 2016 – May 2017 · 1 yr 2 mos · Gainesville, Florida Area

● Developed FPGA-based Custom Memory Cube (CMC) emulation platform leveraging Hybrid Memory Cube (HMC).
● Implemented sorting algorithms on the platform using Micron’s Hyper Threading (HT) language/toolset.
● Designed performance measurement model for the platform.
● This platform enables research on Processor-in-memory, Processor-near-memory and Computational RAM (C-RAM).

FPGASorting AlgorithmsPerformance MeasurementEmbedded SystemsFPGA Development