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BALARAJ M

Product Engineer

Fremont, California, United States7 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in FPGA prototyping and validation.
  • Hands-on experience with H-FPGA and software driver tests.
  • Proficient in developing automation scripts for validation.
Stackforce AI infers this person is a Semiconductor Validation Engineer with expertise in FPGA technologies.

Contact

Skills

Core Skills

Fpga PrototypingAsicValidation

Other Skills

CC (Programming Language)CadenceData AnalysisEmbedded SystemsProFPGA CSProgrammingPythonSynopsys toolsVHDLVLSIVLSI CADVeloceVerilogXilinx ISE

Experience

Siemens eda (siemens digital industries software)

2 roles

FPGA Product Engineer

Jan 2023Present · 3 yrs 2 mos

VerilogFPGA prototypingXilinx VivadoASICProFPGA CSVeloce

FPGA Design Product Engineer

Sep 2021Jan 2023 · 1 yr 4 mos

Intel corporation

4 roles

Pre-Si Valid/Verif Engineer

Feb 2021Aug 2021 · 6 mos

System Validation Engineer

Jun 2019Feb 2021 · 1 yr 8 mos

  • I worked on validating H-FPGA(Hybrid FPGA), hands-on experiences of Simics and Synopsys HAPS 80 FPGA.
  • Developed Bare metal tests(BAT) and validated SPI, I2C, GPIO, UART, AXIDMA, OCS, eMMC, DDR stress testing and PCIe on H-FPGA.
  • Managed Movidebug for running BAT tests on VPU cores.
  • Booted Yocto OS on H-FPGA and validated LSIO software driver tests on H-FPGA, exposure on firmware, software drivers and OS booting on FPGA’s.
  • Release owner of H-FPGA prototype models to software customers, the SW teams use H-FPGA platforms for their driver validation/development in pre-silicon phase before silicon arrives. Developed eMMC test suite to load boot code(Fip) to eMMC boot partitions.
  • Running VCS simulation’s and debugging the bit file models using simulations when failed on emulation platform.
  • Debugging of specific signals in FPGA by instrumentation of FPGA using FPGA protocompiler.
  • Experience in developing C, python and bash scripts for validation of LSIO modules in H-FPGA.
  • Worked on post-silicon platform, exposure on full platform bring up with OS boot. Validated HW & SW driver tests of LSIO on actual Silicon. Exposure in reading platform data sheets, Lauterbatch, T-32, Olimex, probing signals, reading Oscilloscope, Aardvark and protocol samplers or logic analyzers.
  • 3 Department level Awards.

Intern(Post-Si Validation)

Jan 2019Jun 2019 · 5 mos

  • As an Intern, I'm currently working on Emulation platforms to validate hardware by performing Functional safety tests like, MBIST, Safety Mechanism tests and working on JTAG ,I2C protocol, gaining exposure on Firmware API's to integrate with IP's and validate the hardware by emulation techniques.
  • 1 Department level Award.

Intern(Pre-Si Validation)

Jul 2018Jan 2019 · 6 mos

  • As an Intern in Intel I’m working for Functional safety of digital IC’s, my job is to do diagnostic coverage validation using gate level fault simulations, and running the regressions and debugging the regression errors, and coverage analysis. Developed Perl scripts & Bash shell scripts to automate simulation flow tasks, and worked with Synopsys VCS for running simulations and Synopsys Z01X tool to do fault injections and run both logic simulation and Fault simulations on core models in Pri-Si phase.

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Automation Analyst

Mar 2016Apr 2017 · 1 yr 1 mo · Bangalore

  • Worked on automation of different global immigration tools.

Delhivery

Product Analyst

Aug 2015Oct 2015 · 2 mos · Bangalore

  • E-commerce POS software maintenance and automation.

Ifb bangalore, & hal bangalore

INTERNSHIP

May 2014Jun 2014 · 1 mo

  • wireless DC motor control using RF communication(Arduino)

Education

National Institute of Technology Calicut

Master's degree — Microelectronics & Vlsi

Jan 2017Jan 2019

National Institute of Technology Karnataka

Bachelor of Technology (B.Tech.) — Electronics and Communications Engineering

Jan 2011Jan 2015

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