Nov 2018 – Apr 2020 · 1 yr 5 mos · Miami/Fort Lauderdale Area

• System validation and bring-up
• Debugging system software
• Embedded Software Experience
• Worked on DSP's, General Purpose Cores.
• Proficient in C, C++, assembly
• Knowledgable in Electrical Engineering like working with scopes and signal generators and basic circuits.

Feb 2017 – Jul 2018 · 1 yr 5 mos · Tempe

• Generating real-world content for VR is challenging in terms of capturing and processing at high resolution and high frame-rates. The content needs to represent a truly immersive experience, where the user can look around in a 360-degree view and perceive the depth of the scene. The existing solutions only capture and offload the compute load to the server. But offloading large amounts of raw camera feeds takes longer latencies and poses difficulties for real-time applications. By capturing and computing on the edge, we can closely integrate the systems and optimize for low latency. However, moving the traditional stitching algorithms to battery constrained device needs at least three orders of magnitude reduction in power. We believe that the close integration of capture and compute stages will lead to reduced overall system power.
• We approach the problem by building a hardware prototype and characterize the end-to-end system bottlenecks of power and performance. The prototype has 6 IMX274 cameras and uses the Nvidia Jetson TX2 development board for capture and computation. We found that capturing is bottlenecked by sensor power and data-rates across interfaces, whereas compute is limited by the total number of computations per frame. Our characterization shows that redundant capture and redundant computations lead to high power, a huge memory footprint, and high latency. The existing systems lack hardware-software co-design aspects, leading to excessive data transfers across the interfaces and expensive computations within the individual subsystems. Finally, we propose mechanisms to optimize the system for low power and low latency. We emphasize the importance of the co-design of different subsystems to reduce and reuse the data. For example, reusing the motion vectors of the ISP stage reduces the memory footprint of the stereo correspondence stage. Our estimates show that pipelining and parallelization on custom FPGA can achieve real time stitching.

Jul 2013 – Jul 2016 · 3 yrs · Bengaluru Area, India

• Backend IC design flow - block level work in Floor Planning - Placement - Clock-tree Synthesis - Routing - Design Verification
• Static Timing Analysis - ECO fixing - Power Analysis (Static and Dynamic IR Drop)