Deboleena Sakalley

CTO

Hyderabad, Telangana, India23 yrs 7 mos experience
Highly Stable

Key Highlights

  • 18 granted patents in SoC and FPGA architecture.
  • Proven track record in delivering cutting-edge technology solutions.
  • Strong leadership and execution skills in multi-disciplinary teams.
Stackforce AI infers this person is a Semiconductor Architect with extensive experience in FPGA and SoC design.

Contact

Skills

Core Skills

Architecture

Other Skills

AMBA AHBASICAnalytical SkillsDebuggingDigital Signal ProcessorsFPGAFunctional VerificationIPLeadership MentoringLogic SynthesisLow-power DesignPrimetimeRTL DevelopmentRTL codingRTL design

About

Passionate about technology and enjoy working in teams that like to push the envelope. 18 granted patents in the area of SoC, IP and FPGA architecture, flash memory, storage and others. Deep technical background, experience in broad multi-disciplinary areas ranging from technology, architecture, implementation and system level applications coupled with a willingness to learn new areas Strong leadership and execution skills with a proven track record to deliver cutting edge solutions in new technology areas.

Experience

Nvidia

Principal Architect

Jun 2024Present · 1 yr 9 mos · Hyderabad, Telangana, India · Hybrid

Intel corporation

Principal Engineer

Dec 2019Jun 2024 · 4 yrs 6 mos · Greater Hyderabad Area

Architecture

Xilinx

2 roles

Principal Engineer

May 2017Jul 2019 · 2 yrs 2 mos · Greater Hyderabad Area

Senior Staff Design Engineer

Dec 2014Jul 2017 · 2 yrs 7 mos · Greater Hyderabad Area

  • System Architect
  • Architected the Xilinx NVMe Over Fabric solution from scratch. The solution was successfully demonstrated at Flash Memory Summit 2015 and Intel Developers Forum 2015 and generated a lot of interest.

Freescale semiconductor

2 roles

FSL Design Engineer IV

Oct 2014Dec 2014 · 2 mos

FSL Design Engineer III

Sep 2010Sep 2014 · 4 yrs

  • IP Cores RTL Development - Serial protocols
  • Expertise in clocking/reset/power sub-systems
  • Expertise in Clock domain crossing checks using CDC Conformal
  • Expertise in providing STA constraints and exceptions for IP and SoC level
  • Experience in Gate Level Simulation
  • Experience in Debugging Digital components in pre and post silicon validation setup

Stmicroelectronics

3 roles

Engineering Specialist

Jul 2010Sep 2010 · 2 mos

  • Nand/Nor Flash controller IP development
  • Serial Flash controller IP development
  • Memory encryption/decryption module
  • Cache memory microarchitecture

Technical Leader

Aug 2006Sep 2010 · 4 yrs 1 mo

Senior Design Engg

Jan 2002Jan 2008 · 6 yrs

  • FPGA architecture development
  • FPGA DSP core development
  • Updated the VPR place and route tool using C

Stmicroelectronics pvt ltd

Senior design engg

Jan 2002Jan 2008 · 6 yrs

St microelectronics pvt ltd

Senior design engg

Jan 2002Jan 2008 · 6 yrs

Education

Indian Institute of Technology, Bombay

BTech — Electronics

Jan 1998Jan 2002

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