Gaurav Agarwal — Software Engineer

Proven record in verification closure of multiple complex ASICs targeting Data centers , Point of Sale , DFE and wireless market. Extensive cross-functional exposure that helps synergize with Architecture, Design, Silicon Validation and Software teams. Strong hands-on experience on following feature set right from devising Verification strategy and Testbench Architecture to test development and coverage closure. - Secure Boot Architecture for Mobile and POS devices. - PCIe Gen3, Gen5,Gen6 - CXL 1.1 and 2.0 - USB 1.1 and 2.0 interface , OTG devices. - CPRI 4.2 Interface - Cache architecture for ARM, RISC-V , sc140 - Low power architecture. - Coresight Architecture - Various System interconnects and DMA interfaces - RISC-V based cpu subsystems - ARM V7 and V8 based cpu subsystems. - Security architecture (Trustzone+ ,Cryptography, Invasive/Noninvasive attack countermeasures.) Bus Architecture – PCIe , USB, CPRI , CXL , HSI, AMBA (AHB, AXI, APB , CHI) HVL - C , Verilog , System-verilog , UVM

Stackforce AI infers this person is a highly skilled ASIC Engineer with expertise in hardware verification and architecture for data-centric applications.

Location: Bengaluru, Karnataka, India

Experience: 20 yrs 8 mos