Feb 2018 – Sep 2020 · 2 yrs 7 mos · San Francisco Bay Area

• Pathfind Algorithms to support Architectural Innovations in NextGen FPGAs. Modernize Quartus FPGA Compiler. Improve Place & Route QoR, Runtime and Memory.

Jun 2017 – Feb 2018 · 8 mos

Oct 2012 – May 2017 · 4 yrs 7 mos

• Engineering Manager of the Router Group, responsible for the Vivado FPGA Router (route_design). R&D of algorithmic enhancements for performance metrics (timing closure, congestion), Multi-thread and Multi-core scaling and Architecture Optimization. And, in my infinite spare time :), Vivado HLS enthusiast and FPGA/GPU based algorithm acceleration using HLS, SDAccel and OpenCL.

Dec 2008 – Sep 2012 · 3 yrs 9 mos

• Manager of the Core Router Group at Xilinx. Responsible for NextGen Router development that eventually became the highly successful Vivado tool suite, QOR, Runtime and Memory optimization of the Router, Support for Stacked Silicon Interconnect (SSI) FPGAs, ISE Router and Delay Estimator for Virtex7.

Jun 2006 – Nov 2008 · 2 yrs 5 mos

• Router and Delay Estimator R&D for Xilinx ISE software. QOR and Runtime optimization for Xilinx ISE Router, New Architecture support and evaluation (Virtex6 and Spartan6), Congestion modeling and alleviation and Multi-threading for Router. Primary owner of Delay-Estimator, responsible for improving the accuracy of estimates and runtime.

Dec 2003 – May 2006 · 2 yrs 5 mos

• Software development and R&D for FPGA (Field Programmable Gate Array) Placement and Routing. Responsible for Clock Placement, Optimization, Constrained Routing and New Architecture support (Spartan3e and Virtex5).

May 1999 – Sep 1999 · 4 mos · Burlington, MA

• R&D for Datapath placement, specifically Timing and Area Optimization for datapaths.

Jul 1996 – Sep 1997 · 1 yr 2 mos

• Research and development of DSP based systems for Video, Audio and Entertainment applications.