KOUSHIK S K

Product Engineer

Bengaluru, Karnataka, India8 yrs 2 mos experience

Highly Stable

Key Highlights

Expert in Memory Design and Semiconductor Fabrication.
Proven track record in optimizing memory architectures.
Strong background in SRAM design and characterization.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in memory architecture and optimization.

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Skills

Core Skills

Memory DesignSemiconductor Fabrication

Other Skills

Dual Port 8T SRAM DesignMemory CharacterizationRead and Write Margin FixingContention Case AnalysisCritical Path AssessmentMemory ArchitecturesRA CompilersRF CompilersDual Port CompilersAuto-grade CompilersBitcell AnalysisSense AmplifiersAddress DecodersSelf-Timing PathsGlobal Drivers

Experience

8 yrs 2 mos

Total Experience

3 yrs 9 mos

Average Tenure

Current Experience

Mediatek

Memory Design Consultant

Oct 2020 – Feb 2023 · 2 yrs 4 mos · Bengaluru, Karnataka, India

Arm

Memory Design Consultant

Dec 2015 – Sep 2020 · 4 yrs 9 mos · Bengaluru Area, India

In-depth knowledge of various Memory architectures RA compilers, RF compilers, Dual Port compilers, Auto-grade compilers.
Worked across various technology nodes ranging from 55nm MOSFETS to 14nm FINFETS.
Analysis on various critical blocks of memory like Bitcell ADM/WRM sigma qualification, Sense Amplifiers, Address Decoders, Self-Timing Paths and Global Drivers.
Flats V/s Stitched Extraction Netlists Analysis.
Margin optimization for read/write and critical functional margin checks and optimizing the design to meet best competitive PPA.
Characterizing complete compiler in a best effective way for timing, power, leakage and validating the libertys through Data Accuracy[Curve Fitting], Data Validations[Tight Frequency Test] and finally UTC [Trend check across all possible supported options &AMP; corners].
EMIR Analysis to check for max IR drop on power nets / internal driven power nets in layout and fixing them, so that functionality and durability of the chip can be improved.
Post Silicon, Debug of Functionality failures in chip and analysis for the root cause of failures.

Memory ArchitecturesRA CompilersRF CompilersDual Port CompilersAuto-grade CompilersBitcell Analysis+8

Si2chip technologies pvt. ltd.

Senior Design Engineer

Aug 2015 – Feb 2023 · 7 yrs 6 mos · Bengaluru Area, India

Dual Port 8T SRAM [180nm Technology] Design and characterising of Memory, Fixing of read and write Margins, Contention cases, Critical path assessments.

Dual Port 8T SRAM DesignMemory CharacterizationRead and Write Margin FixingContention Case AnalysisCritical Path AssessmentMemory Design+1

Arm

Intern

Oct 2014 – Jun 2015 · 8 mos · Noida

Technology Study on 14nm – FINFET and 28nm – Planar MOS
Transistor Level Characterization: DIBL, GIDL, Leakage Currents, Ion/Ioff trend, Vth variations and subthreshold slope.
Bit-cell stability margins : Read and write stability of bitcell.
Periphery Circuits: Sense amplifier offsets, Level shifters, PG Header Analysis.
Logic study: Delay estimate through logical effort, beta ratios
Aging Degradation Analysis :Aging impact (BTI + HCI) on SRAMs Read and Write margins.

Technology StudyTransistor Level CharacterizationBit-cell Stability MarginsPeriphery Circuits AnalysisLogic StudyAging Degradation Analysis