Prachi Agarwal — Product Engineer
Experienced Static timing analysis engineer with a demonstrated history of working in the VLSI industry. Skilled in constraints development and verification, IO budgeting , ECO flows (PTECO/DMSA), timing closure for multiple power and voltage domains and low power design. Strong engineering professional with a Bachelor's degree focused in Electrical Engineering from Indian Institute of Technology, Kanpur.
Stackforce AI infers this person is a VLSI engineer with expertise in timing analysis and circuit design.
Location: Ajmer, Rajasthan, India
Experience: 6 yrs 8 mos
Skills
- Timing Closure
- Analog Circuit Design
Career Highlights
- Expert in full chip level timing closure.
- Proficient in analog circuit design and simulation.
- Strong background in VLSI industry.
Work Experience
Silicon Physical Design Engineer (1 yr 5 mos)
Intel Corporation
SoC Static Timing Analysis Engineer (5 yrs 2 mos)
Texas Instruments
Summer Research Intern (2 mos)
Efficienergi Consulting Pvt Ltd
Summer Analyst (2 mos)
Education
Bachelor of Technology - BTech at Indian Institute of Technology, Kanpur
